Sriyash Caculo Blog on DSPRelated.com https://www.dsprelated.com/blogs-1/nf/Sriyash_Caculo.php Sriyash Caculo Blog on DSPRelated.com https://www.dsprelated.com/blogs-1/nf/Sriyash_Caculo.php https://d23s79tivgl8me.cloudfront.net/user/profilepictures/128727.jpg en-US Sat, 13 Jun 2026 00:50:03 +0000 1781311803 Project Report : Digital Filter Blocks in MyHDL and their integration in pyFDA https://www.dsprelated.com/showarticle/1194.php The Google Summer of Code 2018 is now in its final stages, and I’d like to take a moment to look back at what goals were accomplished, what remains to be completed and what I have learnt.

The project overview was discussed in the previous blog posts. However this post serves as a guide to anyone who wishes to learn about the project or carry it forward. Hence I will go over the project...]]> Mon, 13 Aug 2018 12:24:03 +0000 Sriyash Caculo Project update-2 : Digital Filter Blocks in MyHDL and their integration in pyFDA https://www.dsprelated.com/showarticle/1189.php This is an exciting update in the sense that it demonstrates a working model of one important aspect of the project: The integration or ‘glue’ between and Pyfda and MyHDL filter blocks. 

So, why do we need to integrate and how do we go about it?

As discussed in earlier posts, the idea is to provide a workflow in Pyfda that automates the process of Implementing a fixpoint filter in VHDL...]]> Mon, 09 Jul 2018 10:45:58 +0000 Sriyash Caculo Project update-1 : Digital Filter Blocks in MyHDL and their integration in pyFDA https://www.dsprelated.com/showarticle/1183.php This blog post presents the progress made up to week 5 in my GSoC project “Digital Filter blocks and their integration in PyFDA”. Progress was made in two areas of the project.

  • Implementation of filter blocks in MyHDL
  • Design of interface between filter blocks and PyFDA

This post will primarily discuss filter block implementation. The interface will be discussed in a later post once...]]> Fri, 22 Jun 2018 13:22:51 +0000 Sriyash Caculo Project introduction: Digital Filter Blocks in MyHDL and their integration in pyFDA https://www.dsprelated.com/showarticle/1176.php Hi everyone! After a lot of hesitation and several failed attempts, I have finally entered the world of blogging. A little about myself : My name is Sriyash Caculo and I’m a third year undergrad student at BITS Pilani K.K. Birla Goa Campus  pursuing a major in Electronics and Instrumentation engineering. Being an electronics engineer, I developed an interest in Digital Signal Processing...]]> Fri, 25 May 2018 13:39:44 +0000 Sriyash Caculo