Residue Number Systems: Algorithms and Architectures (The Springer International Series in Engineering and Computer Scie
There has been continuing interest in the improvement of the speed of Digital Signal processing. The use of Residue Number Systems for the design of DSP systems has been extensively researched in literature. Szabo and Tanaka have popularized this approach through their book published in 1967. Subsequently, Jenkins and Leon have rekindled the interest of researchers in this area in 1978, from which time there have been several efforts to use RNS in practical system implementation. An IEEE Press book has been published in 1986 which was a collection of Papers. It is very interesting to note that in the recent past since 1988, the research activity has received a new thrust with emphasis on VLSI design using non ROM based designs as well as ROM based designs as evidenced by the increased publications in this area. The main advantage in using RNS is that several small word-length Processors are used to perform operations such as addition, multiplication and accumulation, subtraction, thus needing less instruction execution time than that needed in conventional 16 bitl32 bit DSPs. However, the disadvantages of RNS have b. een the difficulty of detection of overflow, sign detection, comparison of two numbers, scaling, and division by arbitrary number, RNS to Binary conversion and Binary to RNS conversion. These operations, unfortunately, are computationally intensive and are time consuming.
Why Read This Book
You should read this book if you need a focused, engineering-oriented treatment of Residue Number Systems for accelerating DSP arithmetic and mapping signal-processing kernels to parallel hardware. It gives you both the mathematical foundations and practical architecture/implementation strategies useful for FPGA/ASIC or accelerator design.
Who Will Benefit
Engineers and researchers designing high-throughput DSP hardware or accelerators who want to apply RNS to arithmetic-intensive tasks such as FFTs, convolutions, and filter implementations.
Level: Advanced — Prerequisites: Familiarity with basic DSP concepts, digital arithmetic (fixed-point), linear algebra/number theory basics (modular arithmetic), and introductory VLSI/FPGA concepts; coding/HDL experience is helpful.
Key Takeaways
- Explain the mathematical basis of residue number systems and the Chinese Remainder Theorem and how they apply to DSP arithmetic.
- Design and select residue bases and modulii appropriate for target dynamic range and error bounds.
- Implement forward and reverse converters and optimize conversion algorithms for latency and hardware cost.
- Map common DSP operations (addition, multiplication, convolution, FFT stages) into RNS to exploit parallelism.
- Evaluate VLSI/FPGA architectures and trade-offs (area, speed, power) for RNS-based DSP blocks.
- Integrate error detection/mitigation and base-extension techniques needed for practical RNS systems.
Topics Covered
- 1. Introduction and historical perspective on Residue Number Systems
- 2. Mathematical foundations: modular arithmetic and the Chinese Remainder Theorem
- 3. Choice of moduli, dynamic range and representational issues
- 4. Forward and reverse conversion algorithms
- 5. RNS arithmetic: addition, subtraction, multiplication and scaling
- 6. Division, base extension, and modular reduction techniques
- 7. Algorithms for convolution and FFTs in RNS
- 8. Error detection, redundancy and robustness in RNS
- 9. VLSI and FPGA implementation strategies
- 10. Case studies: RNS-based DSP kernels and benchmarks
- 11. Design trade-offs, performance analysis and practical considerations
- 12. Conclusions, open problems and references
Languages, Platforms & Tools
How It Compares
Covers similar ground to the classic Szabo & Tanaka treatment but with a much stronger focus on contemporary algorithms and VLSI/FPGA implementation; more architecture-oriented than number-theory textbooks and more comprehensive for implementations than the 1986 IEEE collection.
