Understanding Delta-Sigma Data Converters (IEEE Press Series on Microelectronic Systems)
This new edition introduces operation and design techniques for Sigma-Delta converters in physical and conceptual terms, and includes chapters which explore developments in the field over the last decade
- Includes information on MASH architectures, digital-to-analog converter (DAC) mismatch and mismatch shaping
- Investigates new topics including continuous-time ΔΣ analog-to-digital converters (ADCs) principles and designs, circuit design for both continuous-time and discrete-time ΔΣ ADCs, decimation and interpolation filters, and incremental ADCs
- Provides emphasis on practical design issues for industry professionals
Why Read This Book
You will learn the physical principles and practical design techniques behind modern ΔΣ (delta–sigma) data converters, with clear explanations bridging system-level concepts and circuit implementation. The book emphasizes recent advances — including MASH architectures, mismatch shaping, and continuous‑time ΔΣ ADCs — so you gain up‑to‑date tools to design, analyze, and optimize high‑resolution mixed‑signal converters for real products.
Who Will Benefit
Analog/mixed‑signal IC designers, DSP engineers, and graduate students who need to design or integrate high‑resolution ADCs/DACs and want a practical, modern treatment of ΔΣ converter architectures and implementation tradeoffs.
Level: Advanced — Prerequisites: Solid background in signals and systems (Fourier/DTFT, Nyquist sampling, noise concepts), basic analog circuit theory (op‑amps, RC networks), and familiarity with digital filter concepts (FIR/IIR, multirate filtering); experience with MATLAB/Simulink or SPICE is highly recommended.
Key Takeaways
- Explain the operation and linearized models of ΔΣ modulators and how oversampling plus noise shaping yields high resolution.
- Design and analyze both discrete‑time and continuous‑time ΔΣ ADC front ends, including loop filters and stability margins.
- Implement multi‑stage (MASH) and multi‑bit architectures and apply DAC mismatch shaping and calibration techniques.
- Design decimation and interpolation filter chains optimized for ΔΣ converters and map them to DSP/FPGA implementations.
- Evaluate nonidealities (clock jitter, thermal/quantization noise, circuit nonlinearity) and apply practical mitigation strategies.
- Specify and design incremental and low‑power ΔΣ ADCs for targeted audio, communications, or sensor applications.
Topics Covered
- Introduction and overview of ΔΣ data converters
- Basic principles: oversampling, quantization noise, and noise shaping
- Linearized models, SNR analysis, and performance metrics
- Discrete‑time ΔΣ modulator architectures and loop‑filter design
- Continuous‑time ΔΣ ADCs: principles, benefits, and challenges
- Multi‑stage (MASH) and multi‑bit ΔΣ architectures
- DAC mismatch, mismatch shaping, and digital calibration
- Decimation and interpolation: filter design and implementation
- Incremental and switched‑capacitor ADC topologies
- Nonidealities, stability analysis, and limit cycles
- Practical circuit design considerations and layout issues
- Design examples, measurement techniques, and testing
- Appendices: simulation workflows (MATLAB/Spice), mathematical tools
Languages, Platforms & Tools
How It Compares
Covers similar foundational material as Schreier & Temes' classic treatments but places stronger emphasis on circuit‑level design, continuous‑time ADCs, MASH architectures, and developments from the last decade.
