An analog-to-digital converter (ADC) is a peripheral or standalone IC that samples a continuous analog voltage (or current) and converts it to a discrete digital value proportional to the input. Most MCU-integrated ADCs produce a result in the range of 8 to 16 bits, representing the sampled voltage relative to a reference; 24-bit results are more typical of external delta-sigma converters.
In practice
ADCs appear in nearly every embedded system that interacts with the physical world: reading sensors (temperature, pressure, current, light), digitizing audio, measuring battery voltage, and processing RF or motor-feedback signals. On many mid-range MCUs such as STM32 and nRF52 families, the ADC is a successive-approximation register (SAR) type, commonly running at 12 bits and up to a few Msps, though exact resolution, throughput, and architecture vary by specific device. Higher-precision applications often use external sigma-delta ADCs (e.g., 24-bit parts like the ADS1256 or NAU7802), which trade speed for resolution through heavy oversampling and decimation filtering.
A critical design concern is aliasing: any signal component above half the sample rate (the Nyquist frequency) folds back into the digitized band and cannot be removed after sampling. An anti-aliasing low-pass filter on the analog input is required whenever the input bandwidth is not already limited to below Nyquist. The EmbeddedRelated post "Find Aliased ADC or DAC Harmonics (with animation)" illustrates how aliased harmonics appear in the output spectrum.
Reference voltage accuracy directly sets the conversion accuracy floor. Using a noisy or poorly regulated VREF -- such as tying it directly to VDD without decoupling -- produces proportional errors in every reading regardless of ADC bit depth. Similarly, PCB layout matters: ADC input pins should be routed away from switching signals, and the analog supply domain should be filtered separately from the digital supply on any design where noise budget is tight.
Triggering and DMA are important for efficient use. Most MCU ADCs support hardware triggers from a timer, allowing precise, jitter-free sample rates without CPU involvement in the sample loop. Pairing the ADC with DMA to fill a buffer before raising an interrupt is the standard approach for continuous or high-rate acquisition on bare-metal targets.
Discussed on DSPRelated
Frequently asked
What does ADC resolution (bit depth) actually mean in practice?
An N-bit ADC divides the input range into approximately 2^N discrete quantization levels (the exact count depends on the ADC architecture and code mapping). A 12-bit ADC with a 3.3 V reference has a step size (1 LSB) of about 0.8 mV. Increasing resolution improves the smallest detectable change, but effective resolution is limited by noise; many 12-bit MCU ADCs achieve only 10 to 11 effective number of bits (ENOB) in real circuit conditions.
What is the difference between a SAR ADC and a sigma-delta ADC, and when should I choose one over the other?
A SAR ADC samples the input once per conversion and uses a binary search with a
DAC and comparator, typically producing 8 to 16 bits at sample rates from tens of ksps up to several Msps. A sigma-delta ADC oversamples the input at a high rate with a low-resolution quantizer, then applies a digital
decimation filter to achieve high resolution (16 to 24 bits) at lower output rates. Choose SAR for faster, multi-channel scanning; choose sigma-delta for high-precision, lower-bandwidth applications such as weight scales, precision instrumentation, or audio. The post 'Multi-Decimation Stage Filtering for Sigma Delta ADCs: Design and Optimization' covers the decimation filter design for sigma-delta converters in depth.
Why do I need an anti-aliasing filter before the ADC?
The
Nyquist theorem states that accurate reconstruction requires the input signal to be band-limited below half the
sample rate. Without a filter, high-frequency components -- from interference,
harmonics, or wideband noise -- fold into the
baseband and corrupt the digitized signal in a way that cannot be corrected in software. A simple RC
low-pass filter is often sufficient for slow sensor signals; faster or more demanding applications require a steeper active filter.
How do I get accurate ADC readings on an MCU?
Key practices include: using a stable, low-noise voltage reference (a dedicated VREF pin or external reference IC rather than raw VDD); decoupling VREF and AVDD with capacitors close to the pins; adding a small RC filter (e.g., 100 ohm + 10 nF) on the analog input to limit noise and stabilize the sample-and-hold; allowing sufficient acquisition time before conversion; and averaging or filtering multiple samples in firmware when the signal is slow relative to the
sample rate.
What is the best way to sample at a precise, fixed rate?
On most MCUs, the preferred approach is to configure a hardware timer to trigger the ADC at each period and use DMA to transfer results to a buffer. This eliminates CPU scheduling jitter from the sample timing. Polling in a software loop or triggering from a SysTick ISR introduces variable latency and should be avoided when sample-rate accuracy matters, such as in audio or control loops.
Differentiators vs similar concepts
ADC is sometimes contrasted with
DAC (digital-to-analog converter), which performs the inverse operation. Within ADC types, SAR and sigma-delta are the most common architectures in embedded designs, but flash ADCs (very fast, low resolution, used in RF and oscilloscope-class applications) and pipeline ADCs (intermediate speed and resolution, common in video and communications ICs) also exist. The ADC peripheral on an MCU should not be confused with a standalone precision ADC IC: integrated ADCs prioritize integration and multi-channel flexibility, while external ADCs (e.g., ADS131, MAX11254) optimize for noise performance, resolution, or
sample rate at the cost of an additional chip and communication interface overhead.
