A biquad filter is a second-order recursive digital filter described by a transfer function with two poles and two zeros, implemented using five coefficients (b0, b1, b2, a1, a2). It is the fundamental building block of most IIR filter designs, because higher-order filters are typically constructed by cascading multiple biquad sections rather than implementing a single high-order difference equation directly.
In practice
In embedded DSP work, biquad filters appear wherever signal conditioning is needed: audio equalization, sensor noise rejection, vibration analysis, and motor control feedback loops are common use cases. A single biquad section implements lowpass, highpass, bandpass, notch, peak, or shelving responses depending on the coefficient values. Tools like MATLAB, SciPy, and the web application discussed in "An Astounding Digital Filter Design Application" can generate coefficients directly for a target sample rate and cutoff frequency.
Higher-order responses are achieved by cascading biquad sections in series, a technique called Second-Order Sections (SOS) or biquad cascade. A sixth-order Butterworth lowpass filter, for example, becomes three biquad stages in series. This approach is numerically more stable than implementing a single sixth-order difference equation because each section uses small, well-conditioned coefficients. The blog posts "Design IIR Filters Using Cascaded Biquads" and "IIR Bandpass Filters Using Cascaded Biquads" cover this design flow in detail.
On fixed-point MCUs and DSPs, coefficient quantization and internal accumulator word length matter significantly. Biquad sections are typically computed with 32-bit or 64-bit accumulators to avoid overflow and limit round-off noise, even when input samples are 16-bit. ARM Cortex-M4/M7 cores include a hardware FPU and SIMD MAC instructions; CMSIS-DSP provides optimized biquad routines (arm_biquad_cascade_df1_f32, arm_biquad_cascade_df2T_f32, and fixed-point variants) that leverage these instructions. On smaller 8-bit or 16-bit MCUs without hardware multiply-accumulate, biquad computation is more expensive and may require careful fixed-point scaling.
A practical pitfall is coefficient mismatch between the design sample rate and the actual sample rate of the embedded system. If the ADC or audio codec runs at a slightly different rate than assumed during design, pole and zero locations shift and the filter response degrades. Always verify the actual sample rate on hardware before finalizing coefficients, and consider parameterizing the coefficient calculation so it can be rerun if the sample rate changes.
Discussed on DSPRelated
Frequently asked
What is the difference between Direct Form I and Direct Form II biquad implementations?
Direct Form I uses four delay registers (two for the input side, two for the output side) and is straightforward to implement in fixed-point because the summation happens after all multiplications, giving headroom control. Direct Form II folds the structure to use only two delay registers by sharing the intermediate state, reducing memory but making overflow behavior harder to manage in fixed-point. The transposed Direct Form II (used in CMSIS-DSP
floating-point routines) is often preferred for floating-point implementations due to lower sensitivity to rounding noise, though the best choice can depend on coefficient scaling, target platform, and library implementation.
How many biquad stages do I need for a given filter order?
Each biquad section implements two poles and two zeros, so a filter of order N requires ceil(N/2) biquad stages. An eighth-order elliptic
lowpass needs four cascaded biquads. If N is odd, the implementation typically uses floor(N/2) biquad sections plus one separate first-order section to handle the remaining real pole and zero.
Can a biquad filter implement a notch (band-reject) response?
Yes. Placing a conjugate zero pair on the unit circle at the notch frequency and a conjugate pole pair just inside the unit circle at roughly the same angle produces a notch response. The poles control the notch width: moving them closer to the unit circle narrows the notch. The 'Harmonic Notch Filter' blog post covers a practical embedded application of this technique.
How do I avoid overflow when running a biquad in fixed-point?
The intermediate sum inside the difference equation can exceed the range of the input word length, so the accumulator must be wider than the data path. A common approach on 16-bit data is to use a 32-bit or 64-bit accumulator and scale coefficients to
Q15 or Q31 format. Many DSP cores and ARM Cortex-M4/M7 with DSP extensions provide saturating MAC instructions that help prevent wrap-around overflow. Gain staging between cascaded sections also reduces the chance of intermediate overflow.
Are the same biquad coefficients valid at different sample rates?
No. Biquad coefficients encode frequency as a fraction of the
sample rate. If you design a 1 kHz
lowpass at 48 kHz sample rate and then run the same coefficients at 44.1 kHz, the actual cutoff frequency shifts proportionally (to about 919 Hz in this example) and the response shape may also change. Always redesign or recalculate coefficients for the actual sample rate used in hardware.
Differentiators vs similar concepts
A biquad filter is specifically a second-order
IIR section (two poles, two zeros). An
FIR (Finite
Impulse Response) filter has no feedback poles and is always stable, but achieving a sharp response requires many more taps than a comparable IIR design, making it more computationally expensive for narrow transition bands. A first-order IIR filter (one pole, one zero) is simpler but limited to gentle roll-off slopes. A general high-order IIR filter can be implemented as a single difference equation, but this is numerically fragile in fixed-point and can be susceptible to limit cycles under quantization and saturation conditions; the cascaded-biquad form is preferred in practice for any order above two.
