Decimation is the process of reducing the sample rate of a discrete-time signal by retaining one out of every M samples, where M is the integer decimation factor. In precise DSP usage, decimation refers to the complete process of low-pass filtering followed by that downsampling step (as opposed to downsampling alone, which refers only to the sample-rate reduction). In practice, decimation typically includes a low-pass anti-aliasing filter applied before the sample-rate reduction to prevent aliasing of out-of-band energy into the desired signal band, though some systems rely on bandlimiting applied earlier in the signal chain.
In practice
Decimation appears frequently at the output stage of sigma-delta ADCs, which internally oversample at rates many times higher than the Nyquist frequency of the signal of interest. A decimation filter -- often a CIC (Cascaded Integrator-Comb) stage followed by FIR correction filters -- reduces the sample rate to a more manageable value while shaping and suppressing quantization noise. The blog post "Multi-Decimation Stage Filtering for Sigma Delta ADCs: Design and Optimization" covers this pipeline in detail.
The filter that precedes the downsampler is critical. Without it, frequency components that were originally above the new Nyquist frequency fold back into the baseband, corrupting the signal irreversibly. The filter must attenuate energy in all frequency bands that will alias onto the desired band after downsampling, not only the single band immediately above the new Nyquist. For large decimation factors, a single-stage FIR filter meeting this requirement can have a prohibitively high tap count, which is why multi-stage designs are common: each stage decimates by a smaller factor (often 2), and the filter at each stage is cheaper to implement than one monolithic filter. The blog post "Decimators Using Cascaded Multiplierless Half-band Filters" demonstrates this approach using half-band filters, which require roughly half the multiply operations of a general FIR.
CIC filters are a popular choice for the first decimation stage when the decimation factor is large (commonly 8 to 2048 or more), because they require no multipliers and can run efficiently at the high input sample rate. Their passband droop must be compensated by a downstream filter, however. "Two Easy Ways To Test Multistage CIC Decimation Filters" and "Compute the Frequency Response of a Multistage Decimator" address characterization and verification of these multi-stage chains. The "Instant CIC" post provides a practical implementation reference.
A common pitfall is treating decimation as a pure drop-in operation without auditing the filter's group delay, stopband attenuation, and passband ripple against the application's requirements. Another is forgetting that after decimation the frequency axis rescales: a signal that was at fs/4 before a factor-of-2 decimation appears at fs/2 (the new Nyquist) afterward, which can surprise developers inspecting FFT output.
Frequently asked
What is the difference between decimation and simply throwing away samples?
Keeping every Mth sample without prior filtering is the downsampling step alone. Decimation, as the term is properly used in DSP, combines a
low-pass filter with that downsampling. Skipping the filter causes
aliasing: frequency components above the new
Nyquist frequency fold back into the
baseband and cannot be removed afterward.
Why are CIC filters so often used as the first decimation stage in embedded signal chains?
CIC filters are built entirely from adders, subtractors, and registers -- no multipliers. This makes them very efficient at high input sample rates, which is exactly where the first stage of a sigma-delta
ADC decimation chain operates. The tradeoff is a sinc-shaped passband droop and relatively poor stopband attenuation, so a CIC stage is usually followed by a
FIR compensation filter at the lower, decimated rate.
Why use multiple decimation stages instead of one stage with a large factor?
A single
FIR filter decimating by a large factor M must suppress all aliases while meeting tight transition-band requirements, driving the tap count very high. Breaking the decimation into several stages (each with a smaller factor) allows each per-stage filter to have a wider transition band and fewer taps. The total computational load is typically much lower. Half-band filters are particularly efficient for factor-of-2 stages because nearly half their coefficients are zero.
How do I verify that a multi-stage decimation chain meets its overall frequency response specification?
The overall response is the product (in the
frequency domain) of each stage's filter response, but this requires careful frequency-axis scaling between stages to account for the changing sample rates. You can cascade the responses analytically or simulate the full chain with a known test signal. The blog post 'Compute the
Frequency Response of a Multistage Decimator' walks through the analytical approach, and 'Two Easy Ways To Test Multistage
CIC Decimation Filters' covers practical simulation-based verification.
Does decimation by a non-integer factor require a different approach?
Yes. Non-integer sample-rate reduction is implemented as a rational ratio M/L: the signal is first upsampled (interpolated) by L, low-pass filtered, then downsampled by M. This is called rational resampling. True irrational resampling (e.g., converting between arbitrary audio clock rates) typically uses
polyphase filter banks or asynchronous sample-rate conversion techniques.
Differentiators vs similar concepts
Decimation is sometimes used interchangeably with downsampling, but the terms carry a subtle distinction in precise DSP usage: downsampling refers specifically to the act of keeping every Mth sample (a purely arithmetic operation), while decimation refers to the complete process of filtering followed by downsampling. Using the terms interchangeably is common and generally understood from context, but when discussing filter design it is worth being explicit about whether the anti-
aliasing filter is included.
