A Phase-Locked Loop (PLL) is a feedback control system that drives a local oscillator to match the phase (and therefore frequency) of an incoming reference signal. In DSP contexts, the PLL operates on sampled data, using a phase detector, a digital loop filter, and a controlled oscillator -- typically a numerically controlled oscillator (NCO) -- in place of their analog counterparts.
In practice
Digital PLLs appear in embedded systems wherever a receiver must synchronize to an incoming signal: carrier recovery in software-defined radio (SDR), symbol timing recovery in digital communications, clock recovery from a serial data stream, and locking a local NCO to an external reference clock. The core loop consists of three blocks: a phase detector that computes the phase error between the reference and the NCO output, a loop filter (commonly a proportional-integral filter) that shapes the error signal, and an NCO whose frequency word is updated by the filtered error. The blog series "Digital PLL's -- Part 1" and "Digital PLL's -- Part 2" covers this architecture in detail, and "Digital PLL's, Part 3 -- Phase Lock an NCO to an External Clock" walks through a concrete implementation of locking an NCO to an external clock signal.
Loop filter design is the central trade-off in a digital PLL. A wider loop bandwidth lets the PLL track frequency changes and acquire lock faster, but it also passes more noise through to the NCO, increasing phase jitter. A narrow bandwidth rejects noise well but slows acquisition and may lose lock if the reference frequency varies quickly. On resource-constrained MCUs, the loop filter is often a first- or second-order IIR structure that fits in a handful of multiply-accumulate operations per sample.
A key pitfall in discrete-time PLLs is aliasing in the phase detector output. If the reference signal contains components near or above half the sampling rate, the phase error estimate becomes ambiguous. "Discrete-Time PLLs, Part 1: Basics" discusses how the discrete-time nature of the loop changes the stability analysis compared to the continuous-time case -- classical analog PLL design equations do not map directly to the digital domain without accounting for sampling effects and the z-domain behavior of the loop filter.
Phase vocoders and pitch-shifting algorithms use PLL-like phase tracking on individual FFT bins to follow the instantaneous phase of each frequency component across frames; "The Phase Vocoder Transform" covers this related application. In hardware-centric embedded designs, a digital PLL in firmware may complement or replace an analog PLL IC when the required center frequency or loop bandwidth falls within the processor's computational budget.
Learn this in DSP Foundations
Discussed on DSPRelated
Frequently asked
What is the difference between an analog PLL and a digital PLL in embedded systems?
An analog PLL uses a voltage-controlled oscillator (VCO), an analog
phase detector (often a mixer or XOR gate), and an RC loop filter operating on continuous-time signals. A digital PLL replaces these with an
NCO, a discrete-time phase detector operating on sampled data, and a digital loop filter running on a processor or FPGA. Digital PLLs are more flexible -- loop
bandwidth and filter coefficients can be changed in software -- but their performance is bounded by the
sample rate and the numerical precision of the phase accumulator and filter arithmetic.
How do you choose the loop filter bandwidth for a digital PLL?
The loop
bandwidth is a trade-off between noise rejection and tracking speed. A wider bandwidth acquires lock faster and tracks frequency variations more closely, but lets more noise through, increasing output
phase jitter. A narrower bandwidth suppresses noise but slows acquisition and reduces the range of frequency offsets the loop can track. In practice, the bandwidth is chosen based on the expected frequency uncertainty of the reference, the noise floor, and the required phase accuracy. Stability analysis should be done in the z-domain rather than borrowing analog PLL formulas directly, since sampling introduces additional phase lag that affects the stability margin.
What causes a digital PLL to fail to acquire lock?
Common causes include: the initial frequency offset between the
NCO and the reference exceeding the loop's pull-in range; the loop filter
bandwidth being too narrow to accumulate enough error signal during acquisition;
phase detector ambiguity when the reference is undersampled or heavily aliased; and arithmetic overflow or wrap-around in the phase accumulator or filter state variables. Some implementations add a frequency detector or a frequency sweep (frequency acquisition aid) to help the loop reach the capture range before the phase detector takes over.
Can a digital PLL be implemented on a small MCU without an FPU?
Yes, though care is needed with
fixed-point arithmetic. The
NCO phase accumulator is typically a 32-bit or wider unsigned integer that wraps naturally, and the loop filter can be reduced to a few integer multiply-accumulate operations. The main concern is coefficient scaling: the proportional and integral gains must be chosen so that the filter state does not overflow and that the least-significant-bit resolution of the frequency update word is fine enough to achieve the target phase accuracy. Many bare-metal implementations on Cortex-M0 or MSP430 class devices use Q-format fixed-point arithmetic for the loop filter.
How does a digital PLL relate to the phase vocoder?
A
phase vocoder tracks the instantaneous phase of each
FFT bin across successive frames, essentially running a phase-unwrapping and frequency-estimation process on each bin that resembles PLL-based phase tracking. The output phase estimate is used to resynthesize the signal at a modified pitch or time scale. The connection is conceptual rather than a direct reuse of PLL code, but understanding PLL phase tracking makes the phase vocoder's bin-phase update equations more intuitive. 'The Phase Vocoder Transform' on EmbeddedRelated covers this in detail.
Differentiators vs similar concepts
A digital PLL (implemented in firmware or an FPGA) is often confused with an analog PLL IC (such as the CD4046, Si5351, or integrated PLLs found in many MCU clock-generation blocks like those in STM32 or RP2040). Analog or hardware PLLs are commonly used for clock synthesis -- for example, as part of a chip's clock-generation block -- and are configured via registers to run continuously in hardware. A digital PLL in the DSP sense is a software algorithm that tracks the
phase of a sampled signal at
baseband or near-baseband rates; its ability to synthesize or control output frequencies depends on the system architecture, and in typical embedded or
SDR implementations it operates well below the frequencies that a dedicated hardware PLL clock synthesizer handles. The two may coexist in the same design: the hardware PLL clocks the
ADC, and the software PLL processes the ADC samples.
