Andrej- Your answer is great -- that must have been some debug battle to figure it out. Just lab work, not in the docs, no obvious...

Andrej- Your answer is great -- that must have been some debug battle to figure it out. Just lab work, not in the docs, no obvious clues... It's gems like this that renew my faith in tech group collaboration. I can give 20 answers on the group, then to see one pop up like this is the reward. Thanks. -Jeff Andrej Novak wrote: > Hi Mitko, > > We had also hard time trying to make

Hi everyone, Here's an update... Version 2.0 has a confirmed bug with memory corruption via EMIF/EHPI. There is a problem...

Hi everyone, Here's an update... Version 2.0 has a confirmed bug with memory corruption via EMIF/EHPI. There is a problem at odd addresses. This bug doesn't occur with a JTAG memory write/read. TI will replace shipped 2.0 with a bug fixed version. Mar

We designed a board based of the 5502, we have a SDRAM on CE0, and a ADC on CE1. When we try and write a value to the address space of the...

We designed a board based of the 5502, we have a SDRAM on CE0, and a ADC on CE1. When we try and write a value to the address space of the ADC, the CE1 line WONT drop. After closer inspection, CE0 wont drop either if a value is written or read from its address space. Any suggestions on why our CE's are not working?

i am a new number of 5509 ,i cannot understand the parrel EMIF boot loader of 5509, a0-a13 and d0-d15 connect with flash, EMIF_ce0--...

i am a new number of 5509 ,i cannot understand the parrel EMIF boot loader of 5509, a0-a13 and d0-d15 connect with flash, EMIF_ce0-- EMIF_ce3(throgh CPLD as 2 address line) and GPIO0-GPIO1 all connect with flash, then get 128K data space(program),what about this method ?

Hi , I am working with TMS320C5509A emif and facing a similar problem. When I write address for CE spaces no Chip select is generated. By...

Hi , I am working with TMS320C5509A emif and facing a similar problem. When I write address for CE spaces no Chip select is generated. By default CE signal for CE space CE1 is generated for any address. I am writing address as shown below. *(int*)0x400000 = 0xFFFF; // CE space 2 as I am using in word mode config Also if I write statement where should i be able to see the data in Memo...

Hi,everyone the TI documents illustrate that two DMA controller can't access the same port simultaneously,and the port defined as DARAM SARAM EMIF...

Hi,everyone the TI documents illustrate that two DMA controller can't access the same port simultaneously,and the port defined as DARAM SARAM EMIF peripheral. so if I implement a program in DARAM spaces use two DMA ????one for read ,anther for write,then their can't work simultaneously in one clock cycle. Could anyone who know about this tell me if my understanding is right? Could CPU and DMA ...

Dear list, I am using custom TMS320VC5501 board. It's using EMIF boot. My application code runs fine either emulator mode or boot mode by...

Dear list, I am using custom TMS320VC5501 board. It's using EMIF boot. My application code runs fine either emulator mode or boot mode by complier and linker under CCS2.21. But when I complier and link it under CCS3.3. It's runing by emulator mode. Under the boot mode, it boots but couldn't run interrupter. The hardware is same and the problem is repeatable. By monitors the GPIO4, ...

Hello all I am trying to run two channels of G.729 vocoder on the c5502 processor. The processor is running at 300 MHz and the external SDRAM (...

Hello all I am trying to run two channels of G.729 vocoder on the c5502 processor. The processor is running at 300 MHz and the external SDRAM ( synchronous interface with the EMIF ), is running at 100 MHz. The complete code (.text) section of G.729 is placed in the external memory. All other sections like the .stack, .const, .cinit, .data are placed inside the inernal memory. I have ena...

Hi, I'm working on a very small piece of code on my c5503 system. I have global Variables: volatile int* adc_1_ptr; int*...

Hi, I'm working on a very small piece of code on my c5503 system. I have global Variables: volatile int* adc_1_ptr; int* adc_data; adc_1_ptr = (volatile int*) 0x0ffffe; // extern ADC on Async-EMIF adc_data = (int*) 0xffC1; // internal memory and the instructions *adc_data++ = *adc_1_ptr; *adc_data++ = *adc_1_ptr;

Hi I have a custom 5502 board. I have been able to write code to it's SDRAM and execute form there. My problems (unexpectedly) are coming from...

Hi I have a custom 5502 board. I have been able to write code to it's SDRAM and execute form there. My problems (unexpectedly) are coming from flash. i can access it's flash when i burn my code in it and using flashburn i also compared the flash contents of my board versus the EVM5502 board and i found that they were the same. My GPIOs are always(before reset adn after reset i have hard...

Hi all, I am currently trying to configure a DMA channel to write to a peripheral chip's FIFO buffer over the EMIF. The chips FIFO...

Hi all, I am currently trying to configure a DMA channel to write to a peripheral chip's FIFO buffer over the EMIF. The chips FIFO provides a FIFO Full flag, whose polarity can be configured. My plan was to connect the FIFO Full signal to the c5510's INT5 input, set up the DMA channel with INT5 as the SYNC event and element synchronisation. However, when I test this, all that h...