Forums Search for: DM642
Some problems with I2C module in DM642
inHi, I have problems configuring the I2C module. after the DM642 is reset, it is not possible at all to write anything to the I2C...
Hi, I have problems configuring the I2C module. after the DM642 is reset, it is not possible at all to write anything to the I2C registers, all registers remain 0. Whatever function of the csl-I2c I call, the registers remain 0. It seems that the I2C is deactivated. The procedure described in spru175 (I2C peripherals reference manual) chap. 7 \'Programming guide\'
Linux : DM642 EVM from Spectum digital(PCI version) ?
Does anybody have pointers to Linux driver for DM642 EVM from Spectum digital(PCI version) ? Thanks in advance! ...
Does anybody have pointers to Linux driver for DM642 EVM from Spectum digital(PCI version) ? Thanks in advance!
DM642 VGA/RGB and Monitor problem
HI !!! I am working on project connected with video Processing. Project was created in simulink and compiled by CCS 3.3. Analog camera is...
HI !!! I am working on project connected with video Processing. Project was created in simulink and compiled by CCS 3.3. Analog camera is connected to composite input of DM642, and to VGA/RGB output connected is computer monitor. When I run a program everything was working well, but next day when i connected everything again i realized that nothing is displayed on the screen. I was sear...
Testing video port on custom board with DM642
Hello Everyone, I am working with a custom design using the DM642. It does not have an ethernet port, so I cannot run the examples provided for...
Hello Everyone, I am working with a custom design using the DM642. It does not have an ethernet port, so I cannot run the examples provided for the EVMDM642 to verify operation of the peripherals. I'm working on video port and McASP operation now. CCS includes an 'mpeg2loopback_dm642' project. With this project I want to change the capture port to VP2 and monitor some register, variable etc...
DM642- Video port, Dual port synched raw driver.
Hi! I'm writing a display driver on dm642. The format I want to transmit is 4:2:2 (y/c), but because I need both mcbsp0 and mcbsp1, I...
Hi! I'm writing a display driver on dm642. The format I want to transmit is 4:2:2 (y/c), but because I need both mcbsp0 and mcbsp1, I cannot run vp0 or vp1 in y/c mode (vp2 is taken for capture). What I want to do is to sync vp1 to vp0, and emulate the y/c format. vp0 could send luminance, and vp1 could send interleaved chrominance. Then I wou
DM642 and Raw Data Capture Mode
inHello All, I am trying to interface the DM642 with a CMOS sensor using Video Port 0. I have been following the example in SPRU629 and for...
Hello All, I am trying to interface the DM642 with a CMOS sensor using Video Port 0. I have been following the example in SPRU629 and for the most part I have the video capture working. The problem is that my data is not being synchronized properly. The sensor I am working with outputs line valid and frame valid synchronization signals. I use the line valid signal for the synchr
Reg. Increase in Jitter when NDK library is used with TI DM642 DSP processor
inHi All, I have been using TI DM642 processor along with a set of libraries that TI has provided. The following is the experiment that I did...
Hi All, I have been using TI DM642 processor along with a set of libraries that TI has provided. The following is the experiment that I did to understand the behavior of TI DSP and NDK library. Whenever signal "X" to DSP is raised from low to high, a HWI function is invoked in my program, which in turn will set signal "Y" high for 5 microseconds (this time is not a concern here) and s...
Porting Linux UDF Files system to DM642
Hi All We're thinking of Porting Linux UDF Files system to DM642. Any idea how much time would it take? Thanx & regards Gautham
Hi All We're thinking of Porting Linux UDF Files system to DM642. Any idea how much time would it take? Thanx & regards Gautham
It generates a wait on DM642 when capture 4 cameras.
Hi, I use 4 cameras on DM642 at the same time. It makes three output for 4 camera source by user. The three processes are not equal period...
Hi, I use 4 cameras on DM642 at the same time. It makes three output for 4 camera source by user. The three processes are not equal period time. For example, A is 1ms, B is 21ms, and C is 28ms. Here, I have a problem when capture video signal. Especially, for FVID_exchange(), it have wait time(? I don't know for an exact terminology). FVID_exchange(camera 1); FVID_exchange(camera 2...
scale-up on the DM642 video port
Hello everyone, I am trying to enable the 2-times hardware scaling feature on the DM642 video port. I am using the EVMDM 642 board to...
Hello everyone, I am trying to enable the 2-times hardware scaling feature on the DM642 video port. I am using the EVMDM 642 board to test this. If the hardware scaling on the input and output video ports are both enabled, things are fine. But a problem occurs if I try to do hardware scaling only at the display port. I get an input CIF image from the SAA 7115, blow it to 352
QDMA Example code for DM642
inHello, Is there an example code for performing QDMA on DM642 available? Please suggest. Thanks Amrut
Hello, Is there an example code for performing QDMA on DM642 available? Please suggest. Thanks Amrut
About DM642 PCI master ok interrupt
Hi, all In order to test pci in DM642 for my application, I wrote a simply test program. The int 13th in IER was enabled, the GIE was...
Hi, all In order to test pci in DM642 for my application, I wrote a simply test program. The int 13th in IER was enabled, the GIE was enabled. The master ok bits in PCIIE was also enabled. Then i configured a MASTER??????PCI transfer from PC to SDRAM. The masterok bit in PCIIS was set, and the right data had arrived in SDRAM(I can debug it through a PC based program). However, the dsp ca
Re: hi
Mayank, The error message seems to incate that for some reason a breakpoint was trying to be cleared at memory address 0xD2D40280. ...
Mayank, The error message seems to incate that for some reason a breakpoint was trying to be cleared at memory address 0xD2D40280. I do not have a DM642 EVM memory map in front of me, but the seems like it might not be within your code space. Take a look at the following: 1. the physical mem map for the DM642 EVM.
Error in DM642 DTA copy
inHi, All. I'm using DM642 to do some image process. I opened two tasks. One is for capture image, the other is for image process, when I want to...
Hi, All. I'm using DM642 to do some image process. I opened two tasks. One is for capture image, the other is for image process, when I want to copy data frome one task to another, I find the data after copy is totally different. Here is my code. In task caputer: #pragma DATA_ALIGN(128) static char buffer[2 * FF_WIDTH * FF_HEIGHT]; void TaskSendSerialData() { char *pBuffer = buffer; .....
Host to DSP Interrupt through PCI for DM642 EVM Problem
inHi, I am using TI provided PCI driver for DM642 EVM card, I was able to download my code correctly, and successfully have my...
Hi, I am using TI provided PCI driver for DM642 EVM card, I was able to download my code correctly, and successfully have my code running after writing 1 to DSPINT in HDCR. I am trying to cause an interrupt for host to DSP after the code is running. I set the HOST
Configuring McBSP for RS-232
inHi, I've e-mailed the group about this before (see "RS-232 on DM642 EVM"). I really have trouble configuring McBSP registers. I'm using a 720...
Hi, I've e-mailed the group about this before (see "RS-232 on DM642 EVM"). I really have trouble configuring McBSP registers. I'm using a 720 MHz DM642 EVM. 1. (SRGR) Is baud=CLKG frequency? Given that CLKG freq=(CPU freq/4)/ (CLKGDV+1), the slowest baud is 703.125 khz? So fast? I need to interface to a hardware with a more modest speed of 19200 or 38400 bit/s. 2. (SRGR) What is the fu...
Reg:Synchronizaion in RAW mode+DM642+Pleae Urgent
inHi All, I am working on capturing video in 8 bit RAW mode on DM642 with Tec well Decoder TW2815. I used VSync as CAPEN signal in RAW mode. ...
Hi All, I am working on capturing video in 8 bit RAW mode on DM642 with Tec well Decoder TW2815. I used VSync as CAPEN signal in RAW mode. Until now, i was able to capture the video, but the video data is not synchronized. That means the first pixel of capture buffer does not the first pixel (first line) of current frame, this leads data is skewed to different offset each time i run the progra...
cannot load program,evm dm642
I have a TI's evm dm642,when load program ,got a error: "data verification failed at address 0x80000*00 please verify target memory...
I have a TI's evm dm642,when load program ,got a error: "data verification failed at address 0x80000*00 please verify target memory and memory map" From the datasheet of evm,SRAM address: 0x8000 0000--0x9000 0000. So I think somthing wrong with the SRAM. anyone help?Please ________________________________________________
Field programing of DM642 boot flash
inWe would like to be able to do remote field updates to the DM642 boot flash. Has anyone done this. I was thinking we could have a...
We would like to be able to do remote field updates to the DM642 boot flash. Has anyone done this. I was thinking we could have a base bootloader locked in flash that never will be overwritten that brings interface up, then runtime image can be in another sector of flash that can be overwritten. I am just worried if box is powered down during flash programing we
Why I can't access to SDRAM via DM642 PCI port?
Hi all: Before plugging my card to pci slot, I tested it in EMIF boot mode through JTAG port, all the chips worked very well. But when I...
Hi all: Before plugging my card to pci slot, I tested it in EMIF boot mode through JTAG port, all the chips worked very well. But when I test the card in pci mode (using the EVMDM642 example pci drvier SIC6XWDM.sys and test app in "\\ti\boards\evmdm642\examples\pci" ), all operations of writing to/ reading from DM642 registers and IRAM seem ok, but just can't operate SDRAM. I didn't use ...