Hi all, I also am using using MPEG-4 simple profile as video algorithm on DM642 platform. Video capture is made possible by using...

Hi all, I also am using using MPEG-4 simple profile as video algorithm on DM642 platform. Video capture is made possible by using generic part saa7115 decoder for capture and vport library. The resolution of capture is D1 (720x576). Frame captured: capFrameBuf-> frame.iFrm.y1; capFrameBuf-> frame.iFrm.cb1; capFrameBuf-> frame.iFrm.cr1; It is turned of 4:2:

Hello, I am trying to connect 2 32-bit sdram chip with emifa of dm642  for that what the register values will be there for setting it.any...

Hello, I am trying to connect 2 32-bit sdram chip with emifa of dm642  for that what the register values will be there for setting it.any one  who try plz give  idea about it.and what is the setting or moderegister as i am using CE0 for sdram connection.

Hi: I'm developing a linux driver for DM642.For testing my driver,I have to develop a simple program for c64. I know the CSL can do some...

Hi: I'm developing a linux driver for DM642.For testing my driver,I have to develop a simple program for c64. I know the CSL can do some register operation.But I want to operate the register directly.For example,I want to write 0x12345678 in some register. How can I do this? Thank you. Is anyone developing a linux driver for DM642,maybe we can exchange our mind.

HI !!! I am working with board DM642 EVM (v3). My VGA output doesn't work, and i don't know why. I don't have another board to compare if it is...

HI !!! I am working with board DM642 EVM (v3). My VGA output doesn't work, and i don't know why. I don't have another board to compare if it is hardware or software problem. So i have question to You. My monitor when is connected to board behaves like unconnected. I mean there is displayed picture which means it is unconnected. My question is : if you connect monitor to vga output of board...

Hi, Does anyone know that how fast mpeg4 decode(or H.263) can be achieved by DM642-600MHz?

Hi, Does anyone know that how fast mpeg4 decode(or H.263) can be achieved by DM642-600MHz?

Hi all,          I have to port H.264  C code on a TI DM642 DSPprocessor(750mhz). Can someone tell me what all steps i need...

Hi all,          I have to port H.264  C code on a TI DM642 DSPprocessor(750mhz). Can someone tell me what all steps i need to follow/takecare to achieve this.   regards bharath      To help you stay safe and secure

Hello everybody, I'm working with DM642 DSP device and I would like to use the DAT CSL module. At present time I'm testing it through the...

Hello everybody, I'm working with DM642 DSP device and I would like to use the DAT CSL module. At present time I'm testing it through the following code: bufLap_loc = (label_type *)MEM_valloc(HEAP_L2SRAM, lx*ly2*sizeof(short int), 0,0); bufGauss_loc = (label_type *)MEM_valloc(HEAP_L2SRAM, lx*ly2*sizeof(short int),0,0); imgy_loc = (pixel_type *)MEM_valloc(HEAP_L2SR...

i have the following queries related to DM642 DSP Eval Board.   I need to process 640 x 480 x 24 bits of data at...

i have the following queries related to DM642 DSP Eval Board.   I need to process 640 x 480 x 24 bits of data at @30fps,thats abt 220 MHz of

Hi all, I've a conflict problem on my board, this is the situation: I've a DM642 DSP, SDRAM and FPGA on my board. SDRAM is mapped on EMIFA...

Hi all, I've a conflict problem on my board, this is the situation: I've a DM642 DSP, SDRAM and FPGA on my board. SDRAM is mapped on EMIFA CE0 FPGA is mapped on EMIFA CE1 I use EDMA controller to transfer my data from FPGA to SDRAM, with this configuration: opt: 0x44BE2001h // Block Synchronized 2D-to-2D Transfer src: 0x90000000 // FPGA address cnt: 20 dst: 0x80001000 // SDRAM addr...

Hi all, Im facing problem while running the code on DM642 board. The error displayed is as follows: Error: Error 0x0000000C/-2044 Error...

Hi all, Im facing problem while running the code on DM642 board. The error displayed is as follows: Error: Error 0x0000000C/-2044 Error during: Register, Break Point, No breakpoint at 0x7D694CA0 Sequence ID: 16 Error Code: -2044 Error Class: 0x0000000C Please could anyone help me out in resolving this problem. Im not able to understand what exactly is the problem as Im new to this do...

Hi, I have a custom DM642 board. I am using the Video Port 2 for Video In. McASP0 for audio and McBSP1 configured as UART. 1).McASP0 +EDMA ( Ch...

Hi, I have a custom DM642 board. I am using the Video Port 2 for Video In. McASP0 for audio and McBSP1 configured as UART. 1).McASP0 +EDMA ( Ch 12 , Ch 13)is configured for audio transmit and receive. The code has been taken from the "echo" Project under the evmDM642 examples for audio and modified. 2). McBSP1 + EDMA( Ch14 , Ch15) is configured as UART for RS485 TX & RX. The problem ...

Hi, I am implementing a fir filter in the DM642 for an NTSC video stream. I am using the DSP_fir_gen filter function in order to run it....

Hi, I am implementing a fir filter in the DM642 for an NTSC video stream. I am using the DSP_fir_gen filter function in order to run it. For the test, I am using a sin x/x signal as an input and the output is display in the oscilloscope. I am testing the frequency response of the impulse. The output display almost shows the typical graph (amplitude vs frequen

Hello, I am porting AAC decoder for DM642. I am facing some problems with profiling. The Cycles incl & cycles excl are not satisfactory....

Hello, I am porting AAC decoder for DM642. I am facing some problems with profiling. The Cycles incl & cycles excl are not satisfactory. Also, the no optimization profile results & optimized profile results are not satisfactory. A function having few lines is showing cycles nearly equal to main. for example For No optimization cycle.CPU: cycle.CPU: cycle.Total: cycle.Total: In...

I am trying to configure the DM642 to use McBSP0 and use VP0 in 10-bit mode. SPRS200L page 68 says this can be done. I actually want to use...

I am trying to configure the DM642 to use McBSP0 and use VP0 in 10-bit mode. SPRS200L page 68 says this can be done. I actually want to use VP0D[19:10] as GPIO pins. How do I set this up? The CHIP_Config structure only lets you disable or enable VP0, not put it in 10-bit mode. From my testing, if I enable McBSP0, I can't use the upper VP0 pins for GPIO. CHIP_Config devCfgReg = { CHIP_P...

Hi, I face an issue while connecting xds560 PCI JTAG emulator to DM642 EVM. I've the xds560 emulator inserted in the PCI slot of the PC and...

Hi, I face an issue while connecting xds560 PCI JTAG emulator to DM642 EVM. I've the xds560 emulator inserted in the PCI slot of the PC and installed the driver for it. When I run the diagnostics of the xds560 emulator, all the tests in the diagnostics gets passed without any issue. In the CCS setup, I configured the DM642XDSEMULATOR option and tried opening the CCS. But I get an ERROR mention...

Hi all, I am testing scaling feature of video port on DM642. Can anyone tell me how to compute the scaling values of luma,chroma.Suppose before...

Hi all, I am testing scaling feature of video port on DM642. Can anyone tell me how to compute the scaling values of luma,chroma.Suppose before scaling i am getting the luma/chroma values as 1,2,3,4,5,6,7,8,9,10,11,12,13,etc Then what would be the equivalent values after scaling is enabled. Thanks and Regards, Mayank Agarwal

Hi all, I am configuring the video port on DM642 for transferring the 352*288 frame size.I have some doubt in configuring the threshold and...

Hi all, I am configuring the video port on DM642 for transferring the 352*288 frame size.I have some doubt in configuring the threshold and event register values. Suppose i want to generate event after 1 line in the above scenario then i have to set the threshold =352(44 double words).In that case total events generated for one frame =288.Then the edma element acount should be set to 352,...

Hi All,   Any recommendations for MJPEG codec to run in the DM642? I would like to run SXGA at 24 Frames/Sec   thanks much, ...

Hi All,   Any recommendations for MJPEG codec to run in the DM642? I would like to run SXGA at 24 Frames/Sec   thanks much,   -Bill

Hi,   I have another problem with I2C in DM642. The following is my code:   I2C_Handle hI2c; I2C_Config i2cCfg; ...

Hi,   I have another problem with I2C in DM642. The following is my code:   I2C_Handle hI2c; I2C_Config i2cCfg; com_init();   CHIP_config( &chipConfig );     //enable I2C module in PERCFG register hI2c = I2C_open(I2C_DEV0, I2C_OPEN_RESET); if ( hI2c != INV

Hi all, I have created 32kbyte cache on dm642, and the other part is SRAM. When i use cpu filled a part of off chip SDRAM(bufferA) with some...

Hi all, I have created 32kbyte cache on dm642, and the other part is SRAM. When i use cpu filled a part of off chip SDRAM(bufferA) with some data, and then i use EDMA to transfer this data from bufferA to a part of on chip SRAM(bufferB), at last i use cpu to copy this data from bufferB to another part of off chip SDRAM(bufferC). The algorithm was like this, for(;;) { use cpu change ...