Forums Search for: EDMA
6711DSK and the audio daughtercard
inHi all, 1) The example code accompanying the PCM3003 daughtercard uses codec polling instead of EDMA or interrupt-driven...
Hi all, 1) The example code accompanying the PCM3003 daughtercard uses codec polling instead of EDMA or interrupt-driven processing. Do you know of any way to use that daughtercard with EDMA? 2) It is stated (as a comment) in 2 example codes that the 6711DSK only
EDMA interface to McBSP
inHi all, I'm new to the C6711DSK and I'm hoping you guys can help me to sort out one or two problems I'm having. I'm...
Hi all, I'm new to the C6711DSK and I'm hoping you guys can help me to sort out one or two problems I'm having. I'm attempting to use the EDMA controller to send and receive data via the McBSP which in turn interfaces to the AIC23EVM codec (which sends and receive
Help Please McBSP+EDMA
inHello all I'm a grad student at UT, Arlington and have been working with the C6711 DSK for the past year. I have been reading...
Hello all I'm a grad student at UT, Arlington and have been working with the C6711 DSK for the past year. I have been reading up on McBSP based communication. I need some help with the EDMA part. I have read spra633a.pdf which talks about configuring the McBSP as a UART.
EDMA chained transfers
I have a question regarding the chained EDMA transfers. I have a series of chained EDMA transfer like CH_0 --> CH_1--> CH_2--> CH_3 -->...
I have a question regarding the chained EDMA transfers. I have a series of chained EDMA transfer like CH_0 --> CH_1--> CH_2--> CH_3 --> CH_4. triggering the transfer CH_0 triggers the subsequent transfers. My question is that if at any moment I disable the channel for CH_0 - 1) will it also stop any ongoing transfer between "CH_2 and CH_3 "or "CH_3 and CH_4".(which got initiated prior to disabl
Unable read CIPR bit
inHi Everybody I have written following code in which I am trying to use EDMA to copy data from one memory location to other. The data is...
Hi Everybody I have written following code in which I am trying to use EDMA to copy data from one memory location to other. The data is successfully being transfered but EDMA doesnt generate interrupt and it is not because of TCINT because TCINT=YES. Anybody has any clue. Your help is very much appreciated Kind Regards Here is the Code for reference /* * ======== main.c ======== *...
EDMA problem
inHi all, we are working on 6211 DSK and having problem with EDMA usage. The problems we are facing are as follows --...
Hi all, we are working on 6211 DSK and having problem with EDMA usage. The problems we are facing are as follows -- channel link -- channel chaining -- The length assigned to an array is not reflected properly in the memory.If we assign 1K, 4k of data i
Servicing McBSP with EDMA
inHello, I would like to service a McBSP with EDMA. The situation is this: I have a daughtercard for a C6713DSK wich has a...
Hello, I would like to service a McBSP with EDMA. The situation is this: I have a daughtercard for a C6713DSK wich has a multiple channel DAC. The McBSP0 is used as the interface between the DAC and the CPU. I want to control 4 channels on the DAC, this means I have to
EDMA -> McBSP0 -> Tx Data
Hi all, I had probs with McBSPs before, and never resolved them. Frustrated, I will attempt for help again. I did examine...
Hi all, I had probs with McBSPs before, and never resolved them. Frustrated, I will attempt for help again. I did examine the example code that CCS comes with for McBSP to McBSP data transfer using a polling method, but would like to use a EDMA/McBSP interrupt con
Re: AW: C6414 EDMA stall, missing McBSP words
inMilan, Glad you are making progress. I haven't been looking for info. on this subject recently, but I did notice that ...
Milan, Glad you are making progress. I haven't been looking for info. on this subject recently, but I did notice that SPRZ191G (C6713 Silicon Errata) has a description of the effect of processor L2 cache operations blocking EDMA transfers. I do seem
EDMA help required
Hi! I m using TI c6414 and working on simulator. I am transfering data using EDMA but it takes too much time. Although I have configured...
Hi! I m using TI c6414 and working on simulator. I am transfering data using EDMA but it takes too much time. Although I have configured it according to documentation. -Will the transfer will improve when i go from simulator to my board as here I have specified the 32-bit transfer but emif-A interface provide 64-bit transfer. Am I right a
Linking in EDMA
inHi all, I am having question reagrding EDMA linking option. In the documentation(spru234,pg1-47 to pg 1-49) for continous...
Hi all, I am having question reagrding EDMA linking option. In the documentation(spru234,pg1-47 to pg 1-49) for continous operation they say that linking shud be enabled and in the example that followed showed that another parameter table has been created with same values except that link addre
EDMA reset
inHi all, I'm using DSKC6713 and I want the DSP to search for a certain sequence of samples in a buffer, received from the McBSP. As...
Hi all, I'm using DSKC6713 and I want the DSP to search for a certain sequence of samples in a buffer, received from the McBSP. As soon as this sequence is found, I want the element count of that channel to start from zero (i.e, some kind of reset to the EDMA channel). Is that
Re: Linked EDMA example?
Sorry to respond before I got any group input. In the immortal words of Maxwell Smart, I was "this close" to having something working. I added...
Sorry to respond before I got any group input. In the immortal words of Maxwell Smart, I was "this close" to having something working. I added EDMA_disableChannel(hEdma); to the beginning of my acquisition step and the successive reads now seem to be working. William C Bonner wrote: > I've got a sequence of items that I'm trying to accomplish with a > linked EDMA sequence. I believe t
Re: DM642 PCI xferTest() says the transfer is done, but it isn't really done...
inHi Clem, yes, the problem is known! It also ras resulted in some grey hairs on my head. I think it would save some time if TI had...
Hi Clem, yes, the problem is known! It also ras resulted in some grey hairs on my head. I think it would save some time if TI had described the problem in the PCI documentation a little bit better. You have to invalidate L2Cache before reading data that was copied through PCI Bus (or through EDMA). PCI copies using EDMA as far as I know. You read
EDMA Setup Question (General)
inHi, Im chaining 3 EDMA blocks transfers. For all 3 blocks, I have specifed the completion interrupt codes (TCC) along...
Hi, Im chaining 3 EDMA blocks transfers. For all 3 blocks, I have specifed the completion interrupt codes (TCC) along with the link address (.rld) of the next block (NULL for the last). For the first block I specified a external interrupt (4) as th
problem setting edma on c6713
Hi all, my name is alex and I have some problem with c6713 edma. I'm trying to run a project taken from the chapter 5 of the ppt presentation...
Hi all, my name is alex and I have some problem with c6713 edma. I'm trying to run a project taken from the chapter 5 of the ppt presentation by Naim Dahnoun...the project is built correctly but i can't see the output from the codec when I run the .out file. please can someone help me? thank you
DM642
inHi, Can any body tell me whether DAT_cpy API uses "DMA" or "EDMA" ? Can any body tell me the difference between DAT_cpy, DMA, EDMA...
Hi, Can any body tell me whether DAT_cpy API uses "DMA" or "EDMA" ? Can any body tell me the difference between DAT_cpy, DMA, EDMA and QDMA?? Thanks, Harsha
HPI and EDMA
inhi, i'm using c6414 connected to MPC8250 by HPI. i have a problem with the HPI bus (or with the EDMA transaction triggered by...
hi, i'm using c6414 connected to MPC8250 by HPI. i have a problem with the HPI bus (or with the EDMA transaction triggered by HPI). it happens occasionally when the DSP is under work load. after an HPI write (32 bit), the PQSR bit of the HPI's priority queue (urgent in my case) stays '0', and the data is not written to the des
Re: HPI and EDMA contention
Nir- > The destination address is 0xbf1e8. I tried "more aligned" addresses, > like 0x70000, but I had the same problem. I even tried...
Nir- > The destination address is 0xbf1e8. I tried "more aligned" addresses, > like 0x70000, but I had the same problem. I even tried address in > external memory. same there. > > The load I'm talikng about is low (5Mbit/sec in and out). > > We use cached external memory space, so this use EDMA. > We us
EDMA transfers between CE spaces of the same EMIF
inHi there. I'm using C6415 in my circuit with the EMIFA connected to an SDRAM on CE0 and an FPGA on CE2 (configured as a programmable synchronous...
Hi there. I'm using C6415 in my circuit with the EMIFA connected to an SDRAM on CE0 and an FPGA on CE2 (configured as a programmable synchronous memory), both having the same bus width (64 bit). I was wondering how an EDMA transfer would work between these two spaces. Since the bus is shared, I'm guessing that part of the data from the source (or all of it) is stored in the DSP's internal memo...