Hello friends, I have a problem with allocation of variables, all global variables (arrays) that I declare and then put into SDRAM using ...

Hello friends, I have a problem with allocation of variables, all global variables (arrays) that I declare and then put into SDRAM using #pragma DATA_SECTION (fjac, "SDRAM"); double fjac[15954]; go into FLASH memory, because their addresses begin from 0x64000000. I have checked that, memory map setup correctly in cdb (bios configuration) file. I'm using TMS320C6416T DSK, where SDRAM be...

Looking at the schematic for the EVMDM642 from TI, I see the following connections between the DSP and SDRAM chips. DSP SDRAM #1 ...

Looking at the schematic for the EVMDM642 from TI, I see the following connections between the DSP and SDRAM chips. DSP SDRAM #1 D0 --\ /---------- D0 \ / / \ D7----/ \--------- D7 D8----------------------D8 D15---------------------D15 D16 --\ /---------- D16 \ / / \ D23----/

In my system I have a FIFO of width 16 bit on EMIFA connected physically on bits D[15..0] . And on the same EMIFA I have an...

In my system I have a FIFO of width 16 bit on EMIFA connected physically on bits D[15..0] . And on the same EMIFA I have an SDRAM width of 64 bit . I wont to transfer the data from the FIFO to the SDRAM . If I will use the PDT feature and EDMA transfer ( It is st

Just wondering about a design I recently saw which had a DM642 interfaced to SDRAM using a 32-bit wide data bus. The SDRAM chip only has a 32-bit...

Just wondering about a design I recently saw which had a DM642 interfaced to SDRAM using a 32-bit wide data bus. The SDRAM chip only has a 32-bit wide bus and the other 32 bits of the DM642 are not used. Not sure why it was designed this way as it only going to slow down the EMIF that much more. Can this design work? Is this going to be problem? Any special commands required on the DM642 to s...

ITS- > Hi, I have a question about TMS320DM642 EMIF related ibis simulation. > Previously I designed a DSP board with TMS320C6713 and all of...

ITS- > Hi, I have a question about TMS320DM642 EMIF related ibis simulation. > Previously I designed a DSP board with TMS320C6713 and all of its > simulations with SDRAM went perfectly ok. > > However when I performed the ibis simulation for a newer board, using > TMS320DM642 EMIF with Micron Technology MT48LC4M32B2 SDRAM, I get some > non-monotonic rise and fall waveform over the data p

Hello, I am trying to connect 2 32-bit sdram chip with emifa of dm642  for that what the register values will be there for setting it.any...

Hello, I am trying to connect 2 32-bit sdram chip with emifa of dm642  for that what the register values will be there for setting it.any one  who try plz give  idea about it.and what is the setting or moderegister as i am using CE0 for sdram connection.

Hi, I have a question about TMS320DM642 EMIF related ibis simulation. Previously I designed a DSP board with TMS320C6713 and all of its...

Hi, I have a question about TMS320DM642 EMIF related ibis simulation. Previously I designed a DSP board with TMS320C6713 and all of its simulations with SDRAM went perfectly ok. However when I performed the ibis simulation for a newer board, using TMS320DM642 EMIF with Micron Technology MT48LC4M32B2 SDRAM, I get some non-monotonic rise and fall waveform over the data pins (AED00 for example)...

Hey, I'm working at one project on TMS320C6416, and I have one strange question.I put a 32bits SDRAM on EMIFA, the high 32bits are not used. When...

Hey, I'm working at one project on TMS320C6416, and I have one strange question.I put a 32bits SDRAM on EMIFA, the high 32bits are not used. When I write to SDRAM in a address, the data in another adrress next 16bytes change all the time. For example, when I write a data in Ox8000 0000, the data in 0x8000 0010 also change. The operation in 0x8000 0010 also effects Ox8000 0000. What's the problem?...

The TMS320C6205GHK200 data sheet (SPRS106E) shows a 3ns minimum hold requirement for the EDx during DSP reads from SDRAM. The 100 to 143...

The TMS320C6205GHK200 data sheet (SPRS106E) shows a 3ns minimum hold requirement for the EDx during DSP reads from SDRAM. The 100 to 143 MHz SDRAMs that I have been able to find have data hold time specifications of 2.5ns. This results in a -500ps data hold margin on DSP SDRAM reads. Faster grade (higher spec.) SDRAMs have even lower data hold specifications making this particula

Hi All, I am using a board based on C6416. Writing to SDRAM is nearly six times slower than reading for same amount of...

Hi All, I am using a board based on C6416. Writing to SDRAM is nearly six times slower than reading for same amount of the data. Could anybody help me for fast writing methods. Thanks. Halil

Dear members I work in C6713dsk, for 32 bit data bus my CPU load is 51% I change operation mode to 16 bit SDRAM, By: Init_EMIF...

Dear members I work in C6713dsk, for 32 bit data bus my CPU load is 51% I change operation mode to 16 bit SDRAM, By: Init_EMIF () { ???. *(int *) EMIF_CE0 = 0Xffffbf93 // for 16 bit SDRAM ??? } In gel file. After changing CPU load increase to 57%. Is C6713 in 16 bit mode SDRAM really? Is changing in CPU load from 51%, in 32 bit mode, to 57%,in 16 bit mode, is reasona

Thanks for your reply. I did try to reduce down my ECLKIN signal to 50MHz to see the effect. But unfortunately i still couln't...

Thanks for your reply. I did try to reduce down my ECLKIN signal to 50MHz to see the effect. But unfortunately i still couln't load any code into my SDRAM, while my PowerOnSelfTest code (runnning from IRAM) was successfully able to read/write on the entire memory of the

Hi all ! I am having trouble using the L2 config register in the C6711 DSK. I try to EDMA data from SDRAM into L2, and do...

Hi all ! I am having trouble using the L2 config register in the C6711 DSK. I try to EDMA data from SDRAM into L2, and do some processing on it. If I configure 16K of L2 to be Cache, and enable caching for the SDRAM (MAR0 = 1), the EDMA does not do the correct tr

Hi together, can somebody help me, how to solve my momentary last problem ?? I can't manage to put my 2 projects to a running...

Hi together, can somebody help me, how to solve my momentary last problem ?? I can't manage to put my 2 projects to a running final one...cause its .text section is about 74k => I have to put it into SDRAM ==>> BUT in this case my ISR (=interrupt sevice routine) does

Dakys- > I got the answer for the max bandwidth of the SDRAM, can you please help in the second question? I believe the DMA transfers would...

Dakys- > I got the answer for the max bandwidth of the SDRAM, can you please help in the second question? I believe the DMA transfers would not take place exactly at the same instant, but instead would appear on a dig scope as interleaved. From a software perspective, they would appear to take place concurrently. Two concurrent transfers could be somewhat slower than if only one transfe

Dear all I've got a problem with the DSK board (c6711), I hope you can help me on this one: when i load and run the POST...

Dear all I've got a problem with the DSK board (c6711), I hope you can help me on this one: when i load and run the POST program, which is included in the examples folder in the TI directory. i can not pass the SDRAM test. the problem happened in the following add

Hi all, I am using ccs2 for 6211 based board. When I am in emulator Mode and if I use break point to my C project(which...

Hi all, I am using ccs2 for 6211 based board. When I am in emulator Mode and if I use break point to my C project(which contains SDRAM configuration files generated by DSP/bIOS, c program to access sdram locations), I will get a message like: ' can't Set Bre

Hi, I have a critical thing to do for my project... I have some code which is been placed in the ISRAM, but there is no room for...

Hi, I have a critical thing to do for my project... I have some code which is been placed in the ISRAM, but there is no room for my code to be placed, hence i should place some of the functions/code in the ISRAM to SDRAM. Can anybody help me regarding this. Regards, Narendra --------------------------------- Now you can chat without downloading messenger. Cli...

Dear All, I am trying to interface an ADC to my C6416 DSK, but canot get it to work. Since I was not able to visualize any kind of signal...

Dear All, I am trying to interface an ADC to my C6416 DSK, but canot get it to work. Since I was not able to visualize any kind of signal variation on WR/, RD/ and other signals, I therefore tryed to use the onboard SDRAM. However, if I thougth it was working at the beginning, I came to the conclusion that it was actually not, since I could not again see any signal variation on the external co...

Hi guys, need HELP!!! I have a project to give to my professor on Wednesday, i'm done with everyting on my c6711DSK board...

Hi guys, need HELP!!! I have a project to give to my professor on Wednesday, i'm done with everyting on my c6711DSK board but i can't load a .mp3 file on the DSK SDRAM memory...the file is really small (just 7 K) but still it doesn't put it into memory... T