I am working on a project that the audio signal is interpolated from 8kHz sampling rate to 48kHz. I am using C6713 DSK broad. I configure...

I am working on a project that the audio signal is interpolated from 8kHz sampling rate to 48kHz. I am using C6713 DSK broad. I configure the AIC32 codec with ADC of 8kHz and DAC of 48kHz. At the same time, I use ping-pong buffer to save incoming and outgoing data. Interpolation is achieved. However, I get the noise output. When I configure AIC32 codec with ADC of 8kHz and DAC of 8...

What means 3rd order architecture and dBA short? It's from codec AIC23's manual: "The ADC sigma-delta modulator features third-order multibit...

What means 3rd order architecture and dBA short? It's from codec AIC23's manual: "The ADC sigma-delta modulator features third-order multibit architecture with up to 90-dBA signal-to-noise ratio (SNR) at audio sampling rates up to 96 kHz, enabling high-fidelity audio recording in a compact, power-saving design. The DAC sigma-delta modulator features a second-order multibit architecture wi...

Hi, In regards to a TMS320C6701 EVM/THS1209 daughterboard setup C6701 EVM: ...

Hi, In regards to a TMS320C6701 EVM/THS1209 daughterboard setup C6701 EVM: http://focus.ti.com/docs/pro d/folders/print/tms320c6701.html THS1209 EVM: