ADI BlackFin 533 Opcode

Started by Ed H. in comp.dsp17 years ago 2 replies

Hi, Anybody have a list a BF533 opcode?? I'm looking for a table of opcode for the BF533. The 48 bits instruction word kind. Just like the...

Hi, Anybody have a list a BF533 opcode?? I'm looking for a table of opcode for the BF533. The 48 bits instruction word kind. Just like the one in ADSP-21161 SHARC DSP Instruction Set Reference. There is not such a table in the BF533 ISR. Why? Somebody suggest me to check the Visual DSP memory view and disassembly window but it looks like 16 bits and 32 bits instruction to me. Does...


counting cycles, blackfin

Started by Anonymous in comp.dsp16 years ago 1 reply

Hi all, I'm new to programming the ADSP-BF533 and I would like to know the recommended way to count the nr of cycles used by a...

Hi all, I'm new to programming the ADSP-BF533 and I would like to know the recommended way to count the nr of cycles used by a function. Here's what I'm doing now: main() { int start, stop, overhead, cycles; start = sysreg_read(reg_CYCLES); stop = sysreg_read(reg_CYCLES); overhead = stop - start; sysreg_write(reg_CYCLES, 0x0); // don't want any overflow st...


BF533 / ISP1761 USB Host enumerating problem

Started by Robson Tovo in comp.dsp14 years ago 3 replies

Hello people. I'm using BlackFin BF533 EZ-Kit with ISP1761 as a USB Host Controller. I could succesfully enumerate the internal root hub...

Hello people. I'm using BlackFin BF533 EZ-Kit with ISP1761 as a USB Host Controller. I could succesfully enumerate the internal root hub thanks to the documentation from NXP: AN10037, AN10054. (BTW, also found out some corrections to AN10037, such as writing HC Status Buffer Register) Well, I can send and receive tokens to the root hub, set its address and power the ports using the SetFe...


different data width?

Started by Anonymous in comp.dsp14 years ago 3 replies

Hi, all In the BDTI's pocket guide, there is a column, Data Width, which divides DSPs into different groups. For TMS320C64x+, the data width...

Hi, all In the BDTI's pocket guide, there is a column, Data Width, which divides DSPs into different groups. For TMS320C64x+, the data width is 8/16 bits. For blackfin, the data width is 16 bits. Registers in these dsp are 32 bits, and 32 bits arithmetic operation is supported. For multiplication, 16bits and 8bits multiplication are both supported. Why the data width for C64x+ is 8/16bi...


BlackFin UDP packet transmission

Started by Pave...@gmail.com in comp.dsp14 years ago

Hello. I have BF537 based board wtih external ethernet tranciever. I setup phy and now i want to transmit UDP packet with payload data...

Hello. I have BF537 based board wtih external ethernet tranciever. I setup phy and now i want to transmit UDP packet with payload data acuired from ADC. I don't want to use ADI driver model or lwIP. In my opinion i want to init descriptor based DMA chain with only UDP data field changing. Give me please info about what is UDP packet data structure i need to transmit. Need i calculate some co...


Basic networking on Blackfin STAMP board

Started by in comp.dsp17 years ago 1 reply

Hi, I'm trying to test some basic networking with my STAMP board. I connect it to Win2k via Hyperterminal, 57600 8N1. Everything goes fine. I...

Hi, I'm trying to test some basic networking with my STAMP board. I connect it to Win2k via Hyperterminal, 57600 8N1. Everything goes fine. I fun /> ifconfig eth0 192.198.1.1 mask 255.255.255.0 My PC is configured with and IP address 192.168.1.95 mask 255.255.255.0, I can check that with > ipconfig But pinging each other device does not pass!!! Not even in u-boot, as was mentioned so


AD1854 problem with BF537 EZ Kit lite

Started by isnithin in comp.dsp13 years ago 1 reply

Hello Everyone, I am developing an audio application using Blackfin BF537 EzKit lite. I have some problems with DAC 1854 Sport interface. I...

Hello Everyone, I am developing an audio application using Blackfin BF537 EzKit lite. I have some problems with DAC 1854 Sport interface. I want to pass the audio data samples via SPORT interface to DAC 1854 without using DMA. I am writing to Sport 0 Tx register on receiving the SPORT0_TX interrup as follows *pSPORT_TX=*(audio_data); Should I need wait to check any status register of SPO...


the proper size of cache line

Started by Anonymous in comp.dsp14 years ago 2 replies

Hi,all Now I am developing video application on Freescale's SC3400 core. I am surprised to find that the size of cache line of Dcache is...

Hi,all Now I am developing video application on Freescale's SC3400 core. I am surprised to find that the size of cache line of Dcache is 256 bytes. If you access uncached memory, it will load 256 bytes into the cache. In my opinion, the size of cache line may be too large and will not efficient in video applications. So I get the manuals of DM642 and Blackfin from website, and find th...


DSP/FPGA/video board?

Started by Georgi Beloev in comp.dsp17 years ago 4 replies

Hi, I'm looking for an inexpensive (up to $1000) development board with the following features: - Relatively fast DSP, e.g., Blackfin. -...

Hi, I'm looking for an inexpensive (up to $1000) development board with the following features: - Relatively fast DSP, e.g., Blackfin. - Mid-range Cyclone II or Spartan-3 FPGA. - At least 4 MB SDRAM. - Video in (CVBS and Y/C), digital video decoder. - Video out (CVBS and Y/C), digital video encoder. - The video decoder and encoder should be able to work simultaneously. A combinatio...


Blackfin 536/537 device driver under VDK

Started by MattWang in comp.dsp15 years ago

Anyone has the idea about how to create a new device driver? I create a tcp/ip lwip project and I would like to have a uart driver...how to do...

Anyone has the idea about how to create a new device driver? I create a tcp/ip lwip project and I would like to have a uart driver...how to do it? Except for the driver manager handler for tcp/ip phy driver, should I have another driver manager handler to handle the uart driver?


HD1080p60

Started by HDMI_Vincent in comp.dsp15 years ago

I am looking for a solution (either a DSP or an FPGA) that supports a display rate of 165MHz and above. Does anybody know any DSP supports...

I am looking for a solution (either a DSP or an FPGA) that supports a display rate of 165MHz and above. Does anybody know any DSP supports this high-definition display rate? Blackfin DSPs and TI DSPs only support up to 1080i60 or 1080p30 which requires only 75MHz. I need this high speed for analog component output. My last solution would be an FPGA if none of the DSPs supports this high defini...


when are these dsp cores introduced to market?

Started by Anonymous in comp.dsp14 years ago 6 replies

Hi, I hope to find when the dsp cores from TI, ADI, and Freescale are introduced to market? I searched the internet, but haven't found...

Hi, I hope to find when the dsp cores from TI, ADI, and Freescale are introduced to market? I searched the internet, but haven't found the useful information. For TI, it seems that it first introduced C62x of C6000 seires to market in 1999. C64, C64+ and C67? For ADI, blackfin was introduced to market in 2003? For Freescale, when was SC140 introduced to market? I hope to learn the his...


ADSP 218x SPORT Timings

Started by Nagaraj in comp.dsp17 years ago 1 reply

Hi group, Has anybody worked on internal SCLK, External TFS and RFS configuration in ADSP 218x? If so, does SPORT timings given in...

Hi group, Has anybody worked on internal SCLK, External TFS and RFS configuration in ADSP 218x? If so, does SPORT timings given in data sheet for external SCLK still hold for internal SCLK? Basically I am concerned because Blackfin data sheet gives different timings for external and internal SCLK, but there is no such thing specified in 218x data sheet Could somebody help? Regard...


Inverse FFT of real input on Blackfin

Started by John in comp.dsp18 years ago 1 reply

Hello all, I see that the DSP library has two functions for forward FFT of real input, namely rfft_fr16 and rfftrad4_fr16. Those two take...

Hello all, I see that the DSP library has two functions for forward FFT of real input, namely rfft_fr16 and rfftrad4_fr16. Those two take fract16 input and give complex_fract16 output. I do not see any functions for doing the inverse FFT, which should take complex_fract16 input and produce fract16 output. Is there any way of doing the inverse FFT of real input using the DSP library? Than...