Cascaded integrator-comb (CIC) filter question

Started by Rick Lyons in comp.dsp5 years ago 14 replies

Hi Guys, I've been trying to learn about those darned cascaded integrator-comb (CIC) filters and have reviewed Hogenaurer's original...

Hi Guys, I've been trying to learn about those darned cascaded integrator-comb (CIC) filters and have reviewed Hogenaurer's original paper Hogenauer, E. "An Economical Class of Digital Filters For Decimation and Interpolation," IEEE Trans. Acoust. Speech and Signal Proc., Vol. ASSP?29, pp. 155-162, April 1981. and Matt Donadio's CIC write-up (on www.dspguru.com). ...


Decimation (CIC) filter in VHDL

Started by Ahmad in comp.dsp14 years ago 4 replies

Hi all, I am currently in the process of designing a decimation filter for a 16bit Sigma Delta ADC. I suspect it will be a CIC filter...

Hi all, I am currently in the process of designing a decimation filter for a 16bit Sigma Delta ADC. I suspect it will be a CIC filter followed by a FIR filter. I am facing great difficulty understanding such filter, as my experience in usually with analog circuits, and not DSP. My question basically, is there any free Matlab or VHDL code to get me started simulating either the whole...


CIC Compensating filter

Started by Eric C. in comp.dsp14 years ago 2 replies

I'm designing a CIC filter to perform a hardware efficient downsample. My application is a little bit different in that the downsample...

I'm designing a CIC filter to perform a hardware efficient downsample. My application is a little bit different in that the downsample factor isn't very large, we're just doing a CIC in order to save multiplies in the FPGA. I'm running into problems with the compensating filter, however. So far I've looked at a paper that describes using and integrated second order polynomial (ISOP) for th...


CIC filter

Started by Eng Gan in comp.dsp13 years ago 2 replies

Hi, Can any of you please help me with the question below? Some paper said that CIC filter has a high gain and needed to be compensated? From...

Hi, Can any of you please help me with the question below? Some paper said that CIC filter has a high gain and needed to be compensated? From Mattew P. Donadio: "For a CIC decimator, the normalized gain at the output of the last comb lies in the interval of 1/2 and 1. When R (decimation ratio) is a power of two, the gain is unity" So which one is correct high gain or unity gain? Thanks,...


CIC filter question (a DC offset at the CIC filter output?)

Started by Vincent Ma in comp.dsp13 years ago 1 reply

Dear friends, I am implemeting a CIC filter for a Delta-Sigma ADC, my question is that (assuming the CIC filter has one pair of integrater...

Dear friends, I am implemeting a CIC filter for a Delta-Sigma ADC, my question is that (assuming the CIC filter has one pair of integrater and comb). Since the input is one bit (0 or 1), the output of the intergrator will always be that the following sample is larger or equal to the previous sample. And at the comb part, it subtracts the consecutive two samples and the result must be alw...


CIC filters

Started by Piotr Wyderski in comp.dsp12 years ago 2 replies

Hello, I'm going to implement a decimating CIC filter (inside an FPGA chip), but there are three unclear details. Could you please explain me...

Hello, I'm going to implement a decimating CIC filter (inside an FPGA chip), but there are three unclear details. Could you please explain me them? 1. How should I connect integrators (and combs)? The number of accumulator bits (let's call it N) can be easily computed, but how wide should be the buses interconnecting CIC stages? Should I pass all N bits between every n-th and (n+1)-th st...


CIC Filter design for multiple FM carrier demod

Started by Paul Solomon in comp.dsp12 years ago 22 replies

Hi All, I am working on a project in which we are attempting to demod multiple (analog) FM radio stations in a FPGA. I have been trying to...

Hi All, I am working on a project in which we are attempting to demod multiple (analog) FM radio stations in a FPGA. I have been trying to work out how to design the CIC / FIR filter pair in the DDC section of this design. I have a input sampling rate of 80MSPS, which undersamples a clean spectrum of 88 - 108MHz i.e. the FM band. this should give me the FM band at 8 - 28MHz with an a...


CIC Group Delay

Started by Anonymous in comp.dsp12 years ago 26 replies

I would like to know if I can predict what the group delay of a CIC filter is. I have an agressive FIR BPF where the sample rate is 2000 x the...

I would like to know if I can predict what the group delay of a CIC filter is. I have an agressive FIR BPF where the sample rate is 2000 x the filter bandwidth. The group delay is longer than I would like it to be. Could a CIC filter offer a lower group delay? I'll need to interpolate back to the original sample rate, so I need to take that into consideration as part of the answer. Th...


CIC filter question

Started by AAA in comp.dsp11 years ago 34 replies

I try to understand how CIC decimator works in presence of DC offset of any kind at its input? Filter of that tipe passes through all low...

I try to understand how CIC decimator works in presence of DC offset of any kind at its input? Filter of that tipe passes through all low frequencies including zero, but integrator stages may be overflowed by DC or low frequencies. How to prevent this in practice? Excuse me my english, please help! Thank you in advance. Alex.


poor constellation after CIC filter

Started by fahim in comp.dsp11 years ago

I am trying to simulate a rational sample rate conversion architetcure using CIC filters (decimation) and farrow structure (interpolation)....

I am trying to simulate a rational sample rate conversion architetcure using CIC filters (decimation) and farrow structure (interpolation). Input data is QPSK modulated and upsampled by a large factor (325 to be exact). I try to decimate the signal by 125 in three stages. each stage is in turn a CIC (3-stage) decimation (by a factor of 5) filter. However the constellation i get after CIC filter ...


Help: Digital Up Convert(DUC) in FPGA.

Started by huhu in comp.dsp11 years ago 2 replies

Hi, I am trying to implement a Nicam modulator in a fpga. The Nicam modulation is a digital sound modulation of analog TV, and use DQPSK. I...

Hi, I am trying to implement a Nicam modulator in a fpga. The Nicam modulation is a digital sound modulation of analog TV, and use DQPSK. I have some problem when implement the digital up converter(DUC) in fpga. The DUC comprise the cascade of pulse filter, CIC compensation filter CIC filter, and then multiply with carrier generated by a NCO. The interpolator of the pulse filter and ci...


fixed point CIC filter

Started by sunflowerhj in comp.dsp11 years ago 10 replies

Hi: Can anyone help me to understand why CIC filter can not be implemented in floating point? Mr. Dirk A Bell mentioned: > > A CIC filter...

Hi: Can anyone help me to understand why CIC filter can not be implemented in floating point? Mr. Dirk A Bell mentioned: > > A CIC filter cannot be implemented in floating point. To get it to > > work it must be done in non-saturating integer math, such as is done > > using non-saturating two's complement representation. The integer > > math must wrap around. > > > > Dirk A. Bell in http://www.dsp


application of cic filter

Started by hertfordshire in comp.dsp10 years ago 2 replies

Hey guys I have to design cic interpolation filter using system generator.I am trying to find any single application like in wireless area or in...

Hey guys I have to design cic interpolation filter using system generator.I am trying to find any single application like in wireless area or in audio signal.So can anyone please suggest me?


abt designing cic filter

Started by hertfordshire in comp.dsp10 years ago 2 replies

I have to design cic interpoaltion filter for the application of QPSK modulator.Can anyone suggest me how can i go for that?

I have to design cic interpoaltion filter for the application of QPSK modulator.Can anyone suggest me how can i go for that?


using QPSK modulator

Started by hertfordshire in comp.dsp10 years ago 1 reply

Hey guys, I am designing cic interpolation filter using system genartor.I have gone through xilinx website & try to understand about...

Hey guys, I am designing cic interpolation filter using system genartor.I have gone through xilinx website & try to understand about designing. But still i am confused that how can i implement QPSK modulator like an application of cic filter?can anyone suggest me? or how can i combined qpsk modulator & cic filter? Thanks


my first questions about CIC filter input datatype limit in Matlab

Started by Anonymous in comp.dsp10 years ago 1 reply

hi everyone, when I use FDATools to design a CIC(cascade integrator comb)filter the input datatype must be signed fix point. but after our...

hi everyone, when I use FDATools to design a CIC(cascade integrator comb)filter the input datatype must be signed fix point. but after our sigma delta modulator, the output is in double type. how could I transfer between them in order to use CIC filter in Matlab simulink. forgive me my poor expressions and Thanks a lots zcambrdige


How do I calculate peak value of output from non-unity CIC filter?

Started by G Iveco in comp.dsp10 years ago

My system uses a CIC interpolation (6X) filter. Binary input is fed thru a rcos matched filter with OVS=10, passband BW is B, resulting in...

My system uses a CIC interpolation (6X) filter. Binary input is fed thru a rcos matched filter with OVS=10, passband BW is B, resulting in data D1, which is subsequently interpolated by CIC to 6X times. The amplitude of interpolated output (D2) is lower than matched filter output, which can be explained by the non-uniform gain in the CIC filter. The gain at B is 5dB lower than gain ne...


CIC filter payoff

Started by kungcoccos in comp.dsp10 years ago 7 replies

Hello everyone! Im in the middle of my thesis and one of the objects that the company want to know is: When will a implementation of a CIC...

Hello everyone! Im in the middle of my thesis and one of the objects that the company want to know is: When will a implementation of a CIC filter payoff? After some time spending with such as Hougenauger's and Donadio's publications, I still can't find out when the CIC really gets economical. So to be concrete, the questions are: When does the CIC filter gets economical in terms of int...


CIC filter for sigma-delta converter

Started by ultralowpower in comp.dsp10 years ago 1 reply

Hi, I have one question about the implementation of a CIC decimator filter. How I can meet my especifications of a output range of 16 bits in...

Hi, I have one question about the implementation of a CIC decimator filter. How I can meet my especifications of a output range of 16 bits in the CIC filter output? I have a 2nd order sigma-delta modulator that has a bit stream (1 bit output). Can anyone give me some information about this? The best informations is a CIC filter RTL with explicit one bit input and explicit 16 bits output. I don'...


compensation fir for CIC with interpolate by 2

Started by kungcoccos in comp.dsp10 years ago 3 replies

Hello! My task is: RRC with interpolate by 2 --> CIC compensation with interpolate by 2 --> CIC filter interpolate by 8 The problem is...

Hello! My task is: RRC with interpolate by 2 --> CIC compensation with interpolate by 2 --> CIC filter interpolate by 8 The problem is that I dont know how to make the upsampling in the compensation filter, for now I have written a code in matlab, with compensation for passband droop. step=0.01; fp=[0:step:fo]; fs=[(fo+step):step:0.5]; f=[fp fs]*2; as=ones(1,length(fp)); %gain 1*i