Programming saa7105 video encoder

Started by arichard in comp.dsp12 years ago

Hello, I am trying the examples that came with DM642 evaluation board, and the video drivers are working fine if i want to display a D1...

Hello, I am trying the examples that came with DM642 evaluation board, and the video drivers are working fine if i want to display a D1 frame into a monitor. I am trying to program the saa7105 video encoder to perform scaling from CIF to D1. Did anybody accomplish this task? Can anybody tell me which registers do we have to change in order to perform this? I do know that we have to change...


Dm642 great deal

Started by yigal_fr in comp.dsp14 years ago 8 replies

Hello all, I know about few customers that are really excited about YMagic's offering. At the cost of the H/W design files they almost giving...

Hello all, I know about few customers that are really excited about YMagic's offering. At the cost of the H/W design files they almost giving away: 1. H/W design files 2. A well documented and efficient Board support package 3. MPEG-4 simple profile encoder 4. JPEG encoder Great Deal !!!!!!!!!!!!! For more information enter www.ymagic.com This message was sent using the Comp.DSP...


DM642 Video capture issue

Started by jerome in comp.dsp14 years ago 11 replies

Hi, As I said it in another post we currently work on a card which includes a DSP TI TMS320DM642, a video decoder (SAA7118), SDRAM,...

Hi, As I said it in another post we currently work on a card which includes a DSP TI TMS320DM642, a video decoder (SAA7118), SDRAM, etc.... Our aim is to capture a NTSC YUV video, save it and later compress it. Until now we've succeeded in configuring the registers of the video decoder; the output video data are as expected so this part has been validated. To capture these video data w...


TMS320DM642 8bit QDMA transfers and subsampling

Started by Mark Robinson in comp.dsp14 years ago 5 replies

Hi all. I'm using a DM642 to capture a PAL frame from a video port as 8 bit YCbCr. I want to subsample this frame by half, but I can't use...

Hi all. I'm using a DM642 to capture a PAL frame from a video port as 8 bit YCbCr. I want to subsample this frame by half, but I can't use the video port scaler because I need the full frame too. I tried this using 8 bit QDMA transfers set up as indexed source/incremented dest. The problem is that this is the probably the most inefficient use of the EDMA engine possible, and the whole th...


TI Assembly code problems

Started by salaria in comp.dsp13 years ago 4 replies

Hello, I have been using CCS 3.1 for EVM DM642. I have the following doubts about TI assembly code: 1. What is the difference between linear...

Hello, I have been using CCS 3.1 for EVM DM642. I have the following doubts about TI assembly code: 1. What is the difference between linear code and asssembly code? which one should be stored as .sa and which one should be stored as .asm? There is an assembly optimizer in CCS. Which of these does the optimizer optimize? 2. I have written a small function(procedure) in assembly and call i...


TI BIOS's GIO_submit()

Started by Randy Yates in comp.dsp14 years ago 2 replies

I'm trying to debug a video decoder device driver on a DM642 system that uses TI's class/IOM driver model under BIOS and in which the class...

I'm trying to debug a video decoder device driver on a DM642 system that uses TI's class/IOM driver model under BIOS and in which the class driver is GIO. When the application first starts a video capture, it calls GIO_submit() to obtain a buffer of data, but the function call isn't returning, i.e., it appears to block. The problem is, according to the documentation, the function should ru...


Location of malloc function

Started by keekis in comp.dsp14 years ago 2 replies

Hi! In our project we are using a DM642. We have just recompiled the rtos library. After made some changes to the memory functions, I tried...

Hi! In our project we are using a DM642. We have just recompiled the rtos library. After made some changes to the memory functions, I tried to step into the malloc function. However, the studio does not allow me to do it. In other functions like memset I am able to step into the rtos code. Seems like the code is running another malloc function but I can't figure out where. It is certainl...


problem of use IIC Moudle in a DSP/BIOS program on DM642

Started by X.Y. in comp.dsp13 years ago

In order to config on board codecs using IIC moudle (support by CSL API) in a DSP/BIOS program, I add a IIC write sentence behind video mini...

In order to config on board codecs using IIC moudle (support by CSL API) in a DSP/BIOS program, I add a IIC write sentence behind video mini driver's configuration for a simple test like this: FVID_control(disChan, VPORT_CMD_EDC_BASE + EDC_CONFIG, (Ptr)&EVMDM642_vDisParamsSAA7105); addrI2C = 0x88 > > 1; for(i =0; i


Handling NMI in DSP/BIOS (c6000)

Started by Mark Robinson in comp.dsp14 years ago 6 replies

Hi, Is it possible to call a C handler function in response to a NMI in a c6000 (specifically DM642) DSP/BIOS program? What precautions do...

Hi, Is it possible to call a C handler function in response to a NMI in a c6000 (specifically DM642) DSP/BIOS program? What precautions do I need to take since I can't use the DSP/BIOS dispatcher? I'm guessing I need to do a B NRP somewhere, so could I just add B NRP NOP 5 in asm() blocks at the end of my C handler, or is that a no-no? Cheers mark-r -- "Let's meet the pan...


A question about data transfer between SDRAM and L2

Started by Anonymous in comp.dsp11 years ago 3 replies

hi all, i need transfer data between SDRAM and L2 to speedding my program. as we know that we need call function CACHE_wbInvL2 before we...

hi all, i need transfer data between SDRAM and L2 to speedding my program. as we know that we need call function CACHE_wbInvL2 before we call EDMA functions. but when i call CACHE_wbInvL2 as this CACHE_wbInvL2((void*)PixBuffer1, 0x0000ca80, CACHE_WAIT); i get a mistake from compiler: error: identifier "CACHE_WAIT" is undefined. my dsp is dm642 of ti. and the head file tha...


Doubts in converting Ycbcr422 interlaced to Ycbcr420 non-interlaced CIF on DM642 EVM

Started by kcl_008 in comp.dsp14 years ago 1 reply

I use the following Parameters in the evmdm642_vcapparms.c file VPORTCAP_Params.fldOp = VPORT_FLDOP_FRAME SAA7115_ConfParams.inmode =...

I use the following Parameters in the evmdm642_vcapparms.c file VPORTCAP_Params.fldOp = VPORT_FLDOP_FRAME SAA7115_ConfParams.inmode = SAA7115_MODE_NTSC720 SAA7115_ConfParams.outemode = SAA7115_MODE_CIF I detected that capture frame buffer,both the iFrm.cb1 and iFrm.cr1 has a size of 50688 (176 x 288). What should I do to downsample the capture frame to 4:2:0 , CIF standard (chroma 17...


How to use couple many QDMA's?

Started by ramaa in comp.dsp12 years ago 1 reply

Hi everyone, I am working in developing AV player in DM642 environment and Using the QDMA option for moving pixel data between onchip and...

Hi everyone, I am working in developing AV player in DM642 environment and Using the QDMA option for moving pixel data between onchip and external memory.The QDMA deals with now 8 bit element size.I had seen some where in the TI manuals that use of 32 bit element size will lead to optimization.But all is needed to transfer 8 bit pixel data for processing..Then how to optimize the data transfe...


EVDM642 with Virtex 4 VSA DEMO

Started by Anonymous in comp.dsp11 years ago

Hello! I am using the DM642 Evaluation Module . with the XEVM 642 Xillinx Virtex 4 daughter card. We Bought it from Spectrum Digital. I found A...

Hello! I am using the DM642 Evaluation Module . with the XEVM 642 Xillinx Virtex 4 daughter card. We Bought it from Spectrum Digital. I found A demo that called VSA (http://www.xilinx.com/support/ documentation/application_notes/xapp919.pdf) , this demo , created by Xilinx, Is a video example that combines the DSP (TI) and The FPGA(XILINX). Xilinx gives all the HDL source files for the FPGA ...


Reading file on DM642 with CSS 3.0.0.21

Started by keigo in comp.dsp13 years ago 7 replies

Hi, I need to read in a sequence of raw video file (300 frames, 400MB), and perform video encoding on the C6000 dsp board for benchmarking with...

Hi, I need to read in a sequence of raw video file (300 frames, 400MB), and perform video encoding on the C6000 dsp board for benchmarking with known sequences. I tried using 'fopen' and 'fread' to read/encode frame by frame, however the encoding is far too slow. 10 seconds of video took me hours to encode which should not be the case. Is this mainly due to the file I/O thru JTAG? (as i read...


Getting Error message while doing software reset.

Started by harshiddh in comp.dsp12 years ago 1 reply

Hi, Processor : DM642 Tool : CCS3.1 While doing software reset from the CCS3.1, Previously it was working properly and suddenly i...

Hi, Processor : DM642 Tool : CCS3.1 While doing software reset from the CCS3.1, Previously it was working properly and suddenly i am getting error message as Failed Software Reset: Error 0x00000024/-1147 Error during: Register, Execution, It appears that the target is being held in reset. If this is a multi-core system, the master CPU may not be releasing the DSP from reset....


Problem using fastrts64x.lib with DM642 and DSP/BIOS library

Started by Marc Barmettler in comp.dsp12 years ago 1 reply

Hi I am trying to make fasrts work on my TMS320DM642. I am using DSP/BIOS for my program, and when I link rts6400.lib, and error appears...

Hi I am trying to make fasrts work on my TMS320DM642. I am using DSP/BIOS for my program, and when I link rts6400.lib, and error appears saying that some symbols (2) are defined multiple times (-c_int00 and __stack). When i don't link the rts6400.lib and still include fasrts64x.lib, the program compiles but fasrts functions aren't used and there are no improvements for my computation...


how to extend the address bus of the onboard FLASH(4M) of EVM_DM642

Started by X.Y. in comp.dsp13 years ago

I just find that the FLASH is 4M and it has 22 add lines. The add lines[0:18] are connected to the DM642 directly, while [19:21] are connected...

I just find that the FLASH is 4M and it has 22 add lines. The add lines[0:18] are connected to the DM642 directly, while [19:21] are connected to FPGA. I guess that they use the FPGA as a address decoder to implement paging. However, I don't know how it decode. I mean that what the logic is. Are there any other pin of EMIF connected to the FPGA and used in the decode logic?


BOOT greater than 512KB

Started by tokeiro in comp.dsp12 years ago

Dear all. We have a DM642 based card, and we build an aplication and then we convert coff file to ascii hex to program flash. But the hex file...

Dear all. We have a DM642 based card, and we build an aplication and then we convert coff file to ascii hex to program flash. But the hex file it's greater than 512 KB. We need to select on boot.asm external address to cover range greater than 512KB of the flash. We have a CPLD that has a register ,located at 0xA000081,that manages external address like A19 to A24. What modifications i have ...


the proper size of cache line

Started by Anonymous in comp.dsp12 years ago 2 replies

Hi,all Now I am developing video application on Freescale's SC3400 core. I am surprised to find that the size of cache line of Dcache is...

Hi,all Now I am developing video application on Freescale's SC3400 core. I am surprised to find that the size of cache line of Dcache is 256 bytes. If you access uncached memory, it will load 256 bytes into the cache. In my opinion, the size of cache line may be too large and will not efficient in video applications. So I get the manuals of DM642 and Blackfin from website, and find th...


DM642 PCI Master reads not starting

Started by Mark Robinson in comp.dsp13 years ago

Hi DSPers. I want to do a master PCI read from host memory. My test code looks something like this... Uint32 dsp_addr =...

Hi DSPers. I want to do a master PCI read from host memory. My test code looks something like this... Uint32 dsp_addr = 0x81000000; Uint32 host_addr = 0x1ef60000; Uint32 count = 64; Uint32 ctlreg; ... VFDM642_init(); CSL_init(); ... ctlreg = count < < 16; PCI_xfrConfigArgs(dsp_addr, host_addr, ctlreg, PCI_TRCTL_DEFAULT); PCI_xfrStart(PCI_READ_PREF); while (test = PCI_xfr