## Fractional Decimation in DSP

Started by in comp.dsp9 years ago

Hi, Friends! Recently, I have some questions about Fractional Decimation. I think about them for a lot of time, but can't find a good...

Hi, Friends! Recently, I have some questions about Fractional Decimation. I think about them for a lot of time, but can't find a good solution. It comes from my reading Douglas W.Barker's paper "Efficient Resampling Implementations " presented on "Tips&Tricks" IEEE Signal Processing Magazine,2008. I found some interrelated materials in Mr. Fred Harris's book < < Multirate signal proces

## Polyphase decimation filter, is it only a mathematical gimmick?

Started by in comp.dsp13 years ago 5 replies

My decimation filter is 50 taps, and need to decimate by 10 times. First approach is by normal FIR, but latch outputs every 10th cycle. 2nd...

My decimation filter is 50 taps, and need to decimate by 10 times. First approach is by normal FIR, but latch outputs every 10th cycle. 2nd approach is by dividing them into 10 polyphase filters each with 5 taps. Is it correct to say, each decimated output I get from the two approaches comprises of multiplication and summation of the same data and coefficients?

## help with complex decimation and band shifting

Started by in comp.dsp11 years ago 5 replies

Hi there, I am working in the frequency domain and this must be done in the frequency domain. I have a signal that I would like to decimate...

Hi there, I am working in the frequency domain and this must be done in the frequency domain. I have a signal that I would like to decimate by a factor of 4. Do I simply keep every 4th bin and keep it at that? Would I have to apply a lowpass filter in order to prevent aliasing? If so, how to do I determine the correct lowpass filter to use? After my complex decimation, I need to do a b...

## Decimation (CIC) filter in VHDL

Started by in comp.dsp16 years ago 4 replies

Hi all, I am currently in the process of designing a decimation filter for a 16bit Sigma Delta ADC. I suspect it will be a CIC filter...

Hi all, I am currently in the process of designing a decimation filter for a 16bit Sigma Delta ADC. I suspect it will be a CIC filter followed by a FIR filter. I am facing great difficulty understanding such filter, as my experience in usually with analog circuits, and not DSP. My question basically, is there any free Matlab or VHDL code to get me started simulating either the whole...

## decimation filter (is this normal)??

Started by in comp.dsp16 years ago 2 replies

Hi everybody, I am designing a decimation filter for a 16bit delta-sigma A/D. The decimator will be a CIC decimate by 16 filter, followed...

Hi everybody, I am designing a decimation filter for a 16bit delta-sigma A/D. The decimator will be a CIC decimate by 16 filter, followed by two FIR filters to get the required attenuation. I have two questions as most of my experience is in analog & not digital design. 1- The filter order of the FIR filters is about 100 or 150, is this normal or too much?? 2- The multiplier seems ...

## Low memory footprint decimation

Started by in comp.dsp2 years ago

Hello, so I finally have some time to return to the problem of the multichannel decimation on PSOC5LP. The situation is as follows: there are...

Hello, so I finally have some time to return to the problem of the multichannel decimation on PSOC5LP. The situation is as follows: there are 8 channels of 12 bits@100kHz each and a single digital quadrature mixer running at 310kHz, also 12 bits. The hardware is an 80MHz ARM CortexM3 equipped with a coprocessor called DFB, running at the same speed, with single-cycle 24x24-> 48-bit MAC an

## Multirate filter design

Started by in comp.dsp13 years ago 6 replies

Hello All, The task is to design the multiple cascaded FIR filters to do the decimation. There are tough requirements about the resultant...

Hello All, The task is to design the multiple cascaded FIR filters to do the decimation. There are tough requirements about the resultant ripples in the passband; the stage-by-stage design seems to be very inefficient. Can you suggest a filter design software which can optimize the overall response of the cascaded decimator? Also it would be nice if it can find the optimal decimation...

## Chroma Decimation in Digital Video Signals

Started by in comp.dsp14 years ago 31 replies

Hi, I've seen several cases where the chroma decimation, e.g., when going from YCrCb 4:4:4 to 4:2:2, is done by simply throwing away every...

Hi, I've seen several cases where the chroma decimation, e.g., when going from YCrCb 4:4:4 to 4:2:2, is done by simply throwing away every other sample. I have two questions regarding this operation: 1. If there were a 1-D signal, simply throwing away every other sample without first filtering would cause (potentially) aliasing. Why doesn't this happen in a chroma signal, or wh...

## best method for implementing an SRC

Started by in comp.dsp12 years ago 1 reply

Hi, i would like to know which is the best method for implementing a integer sample rate converter (decimation /interpolation) in terms of...

Hi, i would like to know which is the best method for implementing a integer sample rate converter (decimation /interpolation) in terms of quality. the conversion rates required are (2,4,8,16) both decimation and interpolation.i had tried with polyphase implementation and lagrange interpolation.lagrange interpolation is too spiky and polyphase resulted in flat signal without images. But i wo...

## Combining multiple CIC decimation filters in series

Started by in comp.dsp7 years ago 32 replies

Hi All I'm designing a CIC filter to be used at high decimation rates (e.g. 4000) and am considering whether it could be beneficial to use more...

Hi All I'm designing a CIC filter to be used at high decimation rates (e.g. 4000) and am considering whether it could be beneficial to use more than CIC filter in series. For example, rather than having one CIC that decimates by 4000 I could use four CICs that decimate by 10, 10, 10 and 4x respectively. I have done some quick calculations that suggest that, if I have 4 CICs decimating by 10/10...

## CIC Decimation Filter: implementation questions

Started by in comp.dsp12 years ago

I read the paper by Hogenhauer , the treatment by Donadio and Rick Lyon's article at...

I read the paper by Hogenhauer , the treatment by Donadio and Rick Lyon's article at http://www.eetimes.com/showArticle.jhtml?articleID=160400592 and still have a basic question about DC gains and bit-allocations for CIC decimators. Please bear with me if this is too basic. I am new to digital implementation/bit allocation stuff. For an N-th order CIC decimator with decimation factor R, the...

## Cic Decimator:How many bits to discard at each stage?

Started by in comp.dsp8 years ago 7 replies

Hi, I've read the Reference "IEEE Transaction on acoustics, and signal processing" about Cic filters for decimation and interpolation and I...

Hi, I've read the Reference "IEEE Transaction on acoustics, and signal processing" about Cic filters for decimation and interpolation and I found out something not clear to me. Reading the paragraph about the decimation filter, the reference explain that the number of bits to discard at each stage, in order to make the variance from the first 2N sources less than or equal to the variance for th...

## Custom decimation filter from PCM4222 multibit modulator output using an FPGA

Started by in comp.dsp7 years ago 4 replies

Hi ! I'm new to DSP and trying to make smth out of it for a couple of days. I'm familiar with Altera FPGA's -> so far i was rather doing bits...

Hi ! I'm new to DSP and trying to make smth out of it for a couple of days. I'm familiar with Altera FPGA's -> so far i was rather doing bits manipulation, translating one audio proctol (i2s,left-justified, aes/ebu etc.) to another - with the control of external uC. Now i have to design a decimation filter for sigma-delta ADC PCM4222: http://www.ti.com/lit/ds/symlink/pcm4222.pdf

## WiMAX Decimation FIR Filter

Started by in comp.dsp9 years ago 3 replies

Hi, I am working on a WiMAX project. My jobs is to handle ADC/DAC interface. I am not familiar to Signal Processing. So i need...

Hi, I am working on a WiMAX project. My jobs is to handle ADC/DAC interface. I am not familiar to Signal Processing. So i need your experiences about filtering. I have search about WiMAX and decimation a lot. We implement 10 MHz, 1024 FFT WiMAX system. In our design, analog signal is sampled at 40 MHz. Oversampled by 4 times. So in digital world, first we should filter the signal by LPF a...

## A CIC decimation filter question.

Started by in comp.dsp7 years ago 14 replies

Hi Guys, I have a question for any of you who have studied Hogenauer's original paper on cascaded integrator-comb (CIC) digital filters. ...

Hi Guys, I have a question for any of you who have studied Hogenauer's original paper on cascaded integrator-comb (CIC) digital filters. E. Hogenauer, E. "An Economical Class of Digital Filters For Decimation and Interpolation," IEEE Trans. Acoust. Speech and Signal Proc., Vol. ASSP-29, April 1981, pp. 155-162. I'm having a disagreement with the a signal proce...

## poor constellation after CIC filter

Started by in comp.dsp13 years ago

I am trying to simulate a rational sample rate conversion architetcure using CIC filters (decimation) and farrow structure (interpolation)....

I am trying to simulate a rational sample rate conversion architetcure using CIC filters (decimation) and farrow structure (interpolation). Input data is QPSK modulated and upsampled by a large factor (325 to be exact). I try to decimate the signal by 125 in three stages. each stage is in turn a CIC (3-stage) decimation (by a factor of 5) filter. However the constellation i get after CIC filter ...

## Resampling by multistage decimation (Richard Lyons book)

Started by in comp.dsp8 years ago 7 replies

Hello everybody, I am trying to understand the multistage decimation problem stated by Richard Lyons in his book "understanding digital signal...

Hello everybody, I am trying to understand the multistage decimation problem stated by Richard Lyons in his book "understanding digital signal processing" 1st edition, page 306. It is as follows: - We have an input data arriving at 400 kHz and we want to decimate by 100, but we are going to do this in two stage: 50 and 2. - The original signal bandwidth is something greater than 100 kHz, ...

## Combining smaller FFTs

Started by in comp.dsp10 years ago 4 replies

I have followed a previous post where a decimation in time (DIT) method had been used to combine two half-size FFTs into a full size FFT. I tried...

I have followed a previous post where a decimation in time (DIT) method had been used to combine two half-size FFTs into a full size FFT. I tried to adapt this method by using a Decimation In Frequency (DIF) approach. The reason behind this approach is that it is for an FPGA target, and samples are received over consecutive acquisition periods. If a half-size FFT can be performed when half the ...

## just like half band filters are ther 1/3 band filters too?

Started by in comp.dsp8 years ago 5 replies

Hello, Half band filters are good for interpolation and decimation by 2 as they have alternating 0's as their coefficients. ...

Hello, Half band filters are good for interpolation and decimation by 2 as they have alternating 0's as their coefficients. Is there something like 1/3rd band filters for doing interpolation and decimation by 3 with in-between 2 coeffcients being 0? Regards Bharat

## Digiatal Sampling correction Interpolation/Decimation in e OFDM Modem

Started by in comp.dsp12 years ago

Hi all, My project is Digiatal Sampling correction Interpolation/Decimation for application in flexible OFDM Modem. I'm implementing in Matlab...

Hi all, My project is Digiatal Sampling correction Interpolation/Decimation for application in flexible OFDM Modem. I'm implementing in Matlab the 5_taps optimized interpolator which will improve the performance for long data OFDM bursts. I used control parameters basepoint index (m(k)) and fractional interval (mu(k)) (reference to FM Gardners article "Interpolation In Digital Modems---PART1: ...