DDS - PLL hybrid linear sweep synthesizer

Started by Paul Wolf in comp.dsp10 years ago 6 replies
PLL

Dear professionals, I am interested in designing of a DDS / PLL hybrid linear sweep synthesizer. I would like to buy a DDS and PLL from Analog...

Dear professionals, I am interested in designing of a DDS / PLL hybrid linear sweep synthesizer. I would like to buy a DDS and PLL from Analog Devices. In my case the DDS would be able to produce a highly linear frequency chirp from 0 to 400 MHz, but I have to produce an RF chirp of the frequency up to 4 GHz. So I have found the concept of generating the chirp by the DDS and multiplying its fr...


VCO in a PLL

Started by Anonymous in comp.dsp3 years ago 24 replies

An old engineer told me that although in theory you get improvements in demodulating FM via a PLL, in practice you cannot make a VCO which has low...

An old engineer told me that although in theory you get improvements in demodulating FM via a PLL, in practice you cannot make a VCO which has low enough phase noise to compete with say a Quadrature Detector. This is also the feeling in industry. I would have thought that a VCO could be made near perfect with an FPGA nowadays - or am I missing something?


PLL - quadrature output

Started by kbc in comp.dsp15 years ago 4 replies
PLL

Hi Does PLL have a property that under locked state, the output is in quadrature with the reference input ? I know that this is true...

Hi Does PLL have a property that under locked state, the output is in quadrature with the reference input ? I know that this is true if the phase detector is of multiplier/mixer type ( using the approximation sin E ~ E for error E. ) I am asking whether the above property is there for all plls. If yes, why ?? thanks shankar


implementation of PLL

Started by jkm in comp.dsp14 years ago 1 reply

I am a research scholar working in Power System related to Power Electronics devices. In my work I have to use PLL through assembly langeage...

I am a research scholar working in Power System related to Power Electronics devices. In my work I have to use PLL through assembly langeage programming (by TMS320LF2407A EVM board in Code Composer 2000 environment) for detecting the instantanous frequency of a 3ph transmission line. any one can help me to implement the same? regards jkm


PLL based Clock

Started by justinvil1103 in comp.dsp10 years ago 5 replies
PLL

Would someone explain PLL based clock? Phase locked loop Thanks

Would someone explain PLL based clock? Phase locked loop Thanks


PLL noise bandwidth

Started by johnlovestohate in comp.dsp8 years ago 4 replies

Hi, Can someone tell me in a few words what does noise bandwidth in a PLL mean and also suggest me book or papers where I can know more about it....

Hi, Can someone tell me in a few words what does noise bandwidth in a PLL mean and also suggest me book or papers where I can know more about it. I want to write an algorithm for the code tracking loop of a DSSS system and the book 'Software defined GPS and Galileo receiver' that I am referring now discusses this topic. Thanks


How to understand the zero of PLL with integral and proportional path

Started by fl in comp.dsp8 years ago 3 replies

Hi, I am learning PLL from a tutoril. It says the zero has the character, see below. The zero has the transfer function value 0, but I...

Hi, I am learning PLL from a tutoril. It says the zero has the character, see below. The zero has the transfer function value 0, but I cannot arrive the conclusion below. Could you explain it to me more? Thanks in advance. ..................... The “Zero” in the numerator of the closed-loop transfer function is the frequency in radians/s where the gain of the integral and propo


Coherent vs Noncoherent GFSK Demodulation

Started by john in comp.dsp14 years ago 2 replies

Hi, I've been working on demodulation of low-deviation GFSK signals similar to Bluetooth, with h=0.3 and BT=0.5. I have two simulations, one...

Hi, I've been working on demodulation of low-deviation GFSK signals similar to Bluetooth, with h=0.3 and BT=0.5. I have two simulations, one using a discriminator plus integrate and dump, and another with a second order PLL. I am computing BER vs Eb/No for each case. In the PLL case, I expect to see a few dB of improvement compared to the discriminator, but I'm not getting that. I'm either...


Frequency response of a PLL. What does it convey

Started by Ted in comp.dsp15 years ago 2 replies
PLL

The "frequency response of a PLL" is plotted as angle_at_vco_output(s)/angle_of_input_wavefom(s) = a classical 2nd order system described by a...

The "frequency response of a PLL" is plotted as angle_at_vco_output(s)/angle_of_input_wavefom(s) = a classical 2nd order system described by a the "s" transform, where s = jw. Where w is in radians. So what does a plot of this convey. I've read in places that we can interpret the response as a low pass filter etc. But what we have here is not input voltage divided by output volatage, but...


Programming the FLASH - TMS320C2812

Started by BIT in comp.dsp13 years ago 3 replies
PLL

Hi all, I am trying to erase the FLASH of TMS320F2812 using the custom API provided by...

Hi all, I am trying to erase the FLASH of TMS320F2812 using the custom API provided by TI. http://focus.ti.com/dsp/docs/dspplatformscontento.tsp?sectionId=2&familyId=510&tabId=517 In one of the steps it talks about initializing the PLL control register from using software delays. The PLL lock time is 131072 cycles. Any idea how I can write C-code for such a delay. Thanks, Ram ...


Re: Software PLL (SPLL)

Started by Ken Smith in comp.dsp13 years ago

In article , Ron N. wrote: > Mark wrote: > > > A software PLL is based on an NCO and an NCO unlike a VCO has a minimum > > step size...

In article , Ron N. wrote: > Mark wrote: > > > A software PLL is based on an NCO and an NCO unlike a VCO has a minimum > > step size so it can only achieve a number of discrete frequencies, i.e. > > the output frequency is quantized. > > Why do you say this? Perhaps because this is what he has seen. > An NCO is, o


Is 3rd-order PLL capable to track large freq offset

Started by mccatec in comp.dsp8 years ago 4 replies

Hi, all I wrote a small simulation program to evaluate phase tracking performance for 2nd-order digital PLL and 3rd-order digital PLL. Noise...

Hi, all I wrote a small simulation program to evaluate phase tracking performance for 2nd-order digital PLL and 3rd-order digital PLL. Noise bandwidth of 2nd-order loop and 3rd-order loop are 60Hz and 54Hz, respectively. Simulation results indicate that: 1. 2nd-order loop can track large frequency offset, 340Hz for example. The larger frequency offset, the longer time it takes to track the p...


PLL loop bandwidth analysis

Started by jacobfenton in comp.dsp7 years ago 8 replies

Suppose you have a classical 2nd order PLL, but instead of having a linear error curve, with a slope you can determine, you have essentially a...

Suppose you have a classical 2nd order PLL, but instead of having a linear error curve, with a slope you can determine, you have essentially a slope of 0, which means that you can detect error, but only the same value is put out of the detector (with sign changes), perhaps this is what people call bang-bang style. So can you approximate this error gain so you can still use a classical approach to ...


clock system design on ADSP2191M

Started by YG in comp.dsp16 years ago 5 replies

Hello, i want to use a single clock to control the ADSP2191M and an audio codec with a 24.576MHz quartz. Fortunately, the 2191 has a PLL that...

Hello, i want to use a single clock to control the ADSP2191M and an audio codec with a 24.576MHz quartz. Fortunately, the 2191 has a PLL that can do 6.5x so it can reach 159.744MHz, which is pretty near the maximum 160MHz core frequency. But then, things get complicated. it seems that CLKOUT (provided by the 2191) outputs the PLL's frequency, but i want to get the "input" frequency of...


charge pump related loop simulation in PLL

Started by fl in comp.dsp11 months ago 2 replies

Hello all: Though my question is not in the strict DSP, I cannot find another appropriate forum to discuss about it. As a hobby, I am interested...

Hello all: Though my question is not in the strict DSP, I cannot find another appropriate forum to discuss about it. As a hobby, I am interested in a PLL simulation. On numerous tutorials, I know there are current sources in a charge pump type phase detector. I realize that the current source makes the voltage cross the capacitor linearly increase. It is seen the Laplace transform of the RC ...


Re: Software PLL (SPLL)

Started by Ron N. in comp.dsp13 years ago

Mark wrote: > A software PLL is based on an NCO and an NCO unlike a VCO has a minimum > step size so it can only achieve a number of...

Mark wrote: > A software PLL is based on an NCO and an NCO unlike a VCO has a minimum > step size so it can only achieve a number of discrete frequencies, i.e. > the output frequency is quantized. Why do you say this? An NCO is, of course based on some digital number representation; but if you use IEEE doubles, the quantization error of the phase is much smaller than the thermal noise o


SRF-PLL problem

Started by Mimar in comp.dsp6 years ago 19 replies

Hello, can somebody give me an advice? I have decided to use SRF-PLL system for frequency tracking/estimation in 3 phase power grid recently...

Hello, can somebody give me an advice? I have decided to use SRF-PLL system for frequency tracking/estimation in 3 phase power grid recently but there is some problems: 1. long settling time, but I beliave, I will solve this soon 2. if I am trying to change frequency constantly(= frequency ramp), the estimation frequency curve is above reference curve and the distanc of these curves gets bigg...


PLL noise bandwidth

Started by biel_d in comp.dsp10 years ago 4 replies

Hi all, I'm currently start working with DPLL. One design parameter in the development of narrow bandwidth DPLL is the noise bandwidth. I read...

Hi all, I'm currently start working with DPLL. One design parameter in the development of narrow bandwidth DPLL is the noise bandwidth. I read that the noise bandwidth could be calculated as the integral over the closed loop response and I did this but I get a huge value for a narrow bandwidth PLL? Could you please help me or give me a hint where I can find a documentation how I can estimate th...


Z-domain analysis of PLL

Started by algae11 in comp.dsp4 years ago 1 reply
PLL

Hi, For the s-domain analysis, the low pass filter has a minimal state space realization: dxf/dt = Af * xf +Bf *uf yf = Cf *xf The...

Hi, For the s-domain analysis, the low pass filter has a minimal state space realization: dxf/dt = Af * xf +Bf *uf yf = Cf *xf The linear system G(s) is represented by dx/dt= A * x +B *u y = C *x I would like to ask about how to transform the PLL configuration into the Lur'e system, and then find the corresponding G(z)? From there,how to find the state-space matrices A,B,C and D w...


Premodulation filter/PLL loop filter

Started by Jon Mcleod in comp.dsp12 years ago 5 replies

Mayby not the right group, but.. On my bench, I have created an ad-hoc signal generator to drive some old paging receiver boards. I am using...

Mayby not the right group, but.. On my bench, I have created an ad-hoc signal generator to drive some old paging receiver boards. I am using a DDS to generate phase-continuous, 4-level FSK. I'm then "multiplying" the output of the DDS (using a PLL/VCO module) by 11, creating an RF carrier. The output of the VCO is the RF carrier (~929MHz). Doing this, I can actually create a carri...