Scilab bilinear transform

Started by Andrew Holme in comp.dsp12 years ago 5 replies

I'm using Scilab to convert an s-domain filter design to the z-domain for a PLL simulation. It works fine with a time-step of one micro-second...

I'm using Scilab to convert an s-domain filter design to the z-domain for a PLL simulation. It works fine with a time-step of one micro-second (Ts=1e-6): the denominator contains z^4 terms, which I was expecting; and the PLL simulation agrees with the real hardware; but I only get z^3 terms if I reduce the time-step to 1e-7; and the simulation is unstable (it oscillates at 3 KHz). What...


FIFO controlled loop, PLL, FLL or something else?

Started by rickman in comp.dsp10 years ago 16 replies
PLL

I'm sure I'm not the first person to control an oscillator by the amount of data in a FIFO, but I haven't found a reference to this design which...

I'm sure I'm not the first person to control an oscillator by the amount of data in a FIFO, but I haven't found a reference to this design which is similar to a PLL. In place of a typical phase detector, I am using the count of samples in the FIFO to control the DCO which drives the output clock. Data is clocked into the FIFO using the reference (input) clock. I have an integrator betwee...


Designing a loop filter for software PLL with following known information

Started by johnlovestohate in comp.dsp7 years ago 13 replies

Hi, I want to design a software PLL to correct a frequency offset in a baseband BPSK signal and after referring to the book Phase Locked Loops by...

Hi, I want to design a software PLL to correct a frequency offset in a baseband BPSK signal and after referring to the book Phase Locked Loops by Ronald Best I understand most of it. I still have questions regarding designing of the loop filter. L(s) = tau2*s + 1 ___________ tau1*s The laplace transform of the loop filter is as shown above and I can use bilinear transform...


Achievable threshold extension?

Started by PalapaGuy in comp.dsp9 years ago 5 replies
PLL

Back several years ago I implemented a DSP based, PLL FM demod for a satellite downlink application. It achieved about 3 to 4 dB of...

Back several years ago I implemented a DSP based, PLL FM demod for a satellite downlink application. It achieved about 3 to 4 dB of threshold extension over a conventional demod. My question is, can greater extension be achieved using PLL or FMFB techniques in special cases? Specifically, can greater extension be achieved if it is only necessary to recover a narrow portion of the baseband? S...


baudrate dvb with cyclone

Started by phil_07 in comp.dsp12 years ago
PLL

Hi guys, we have a ip working in FPGA StratixII using a reconfigurable pll to generate the correct baud rate output for one DVBS modulator....

Hi guys, we have a ip working in FPGA StratixII using a reconfigurable pll to generate the correct baud rate output for one DVBS modulator. We need reduce cost and we decided migrate to device Altera cycloneII. The problem is that cycloneII fpga there are no reconfigurable PLL. Its possible to generate one counter to generate the output baudrate (1 to 35MSPS - each 1 Kilo symbol) from one in...


PLL Terminology Question

Started by Tim Wescott in comp.dsp6 years ago 72 replies
PLL

How commonly do you see PLL designs referred to as "type I", "type II", "type III", etc.? Do the terms make sense to you? I'm writing a...

How commonly do you see PLL designs referred to as "type I", "type II", "type III", etc.? Do the terms make sense to you? I'm writing a report; don't want to either baffle with bullshit nor leave out handy terms... -- My liberal friends think I'm a conservative kook. My conservative friends think I'm a liberal kook. Why am I not happy that they have found common ground? Tim Wesco...


Stuffing/Skipping in symbol timing synchronization

Started by commsignal in comp.dsp7 years ago 5 replies
PLL

Well, it's a very simple question but I need to ask. When we implement a symbol timing PLL, why do we skip or stuff a sample during...

Well, it's a very simple question but I need to ask. When we implement a symbol timing PLL, why do we skip or stuff a sample during symbol synchronization (based on the relative clock speed) when we are already implementing a second-order filter in the timing PLL? Was not the purpose of 2nd order filter to track and follow the clock frequency mismatch automatically? Thank you.


Help with Digital PLL motor control

Started by Jay in comp.dsp15 years ago 20 replies

Hi everyone. I am working on a digital PLL design for a motor control application and I need some help with the control-loop aspects. The end...

Hi everyone. I am working on a digital PLL design for a motor control application and I need some help with the control-loop aspects. The end goal is to have my motor achieve phase lock with a reference signal. Some background information: My system consists of an FPGA which implements the "digital logic" end of things such as the Frequency/Phase detector + error counters, PWM con...


QPSK Carrier(Frequency) recovery using a PLL in Matlab

Started by Udesh in comp.dsp7 years ago 3 replies

Hi all, I have implemented a carrier (frequency) recovery system in matlab codes using a power 4 PLL (taking the signal to its 4th power to get...

Hi all, I have implemented a carrier (frequency) recovery system in matlab codes using a power 4 PLL (taking the signal to its 4th power to get rid of data signal). I want to analyze the performance of the system at the presence of the noise. But I have some issues regarding the models. I have used a Butterworth low pass filter as the loop filter and an integrator as the VCO. Cou


carrier recovery in software using PLL

Started by mizer03 in comp.dsp11 years ago 7 replies

Hello all! I want to implement QPSK modulation in software. But i know that QPSK signals can only be detected coherently. i.e knowledge of the...

Hello all! I want to implement QPSK modulation in software. But i know that QPSK signals can only be detected coherently. i.e knowledge of the carrier frequency and phase is mandatory for correct detection. How is possible to recover the carrier synchronization in software? Is it possible to implement PLL for carrier recovery and synchronization using software? (the programming language i'm using...


What is the phase margin for a PLL of critically damped?

Started by fl in comp.dsp7 months ago 4 replies

Hello, all: I read an online PLL tutorial, which says "the design of critically damped loops, a PM of about 70 degrees, does not lead to the...

Hello, all: I read an online PLL tutorial, which says "the design of critically damped loops, a PM of about 70 degrees, does not lead to the fastest settling time for third order CP PLLs." It is known that a critically damped second order loop has zeta=1, i.e. two real roots of the same value. But I can't get its phase margin 70 degrees. What do you think about phase margin remark? ...


jitter calculation for ADC

Started by ytach in comp.dsp11 years ago 8 replies
PLL

Hello group, How do I calculate the jitter for an ADC driven by a 125 MHZ. this 125 MHZ is generated by a PLL circuit with 10MHz ref clock that...

Hello group, How do I calculate the jitter for an ADC driven by a 125 MHZ. this 125 MHZ is generated by a PLL circuit with 10MHz ref clock that has 10 ppm. My question really is if the PLL circuit is driven by a clock with a jitter x, will the output jitter be x or will it be magnified?


False phase lock detector for PLL (GPS application domain)

Started by Anonymous in comp.dsp3 years ago 13 replies
PLL

In continuation of the topic I started earlier, which is about the false ph= ase lock in PLL...

In continuation of the topic I started earlier, which is about the false ph= ase lock in PLL (https://groups.google.com/forum/#!topic/comp.dsp/izuEzbew9= 8E). I am trying to implement a false phase lock detector using the approach des= cribed in Kaplan book "Understanding GPS: Principles and Applications": htt= p://tinyurl.com/z27gl4v=20 The idea is to compute the phase angle between the...


Phase Noise of PLL

Started by ckiancho in comp.dsp14 years ago 5 replies

Hi. Phase noise of a PLL is usually specified over a few discrete frequency points. For example, at 10kHz, 30kHz, 100kHz, 1MHz... My question...

Hi. Phase noise of a PLL is usually specified over a few discrete frequency points. For example, at 10kHz, 30kHz, 100kHz, 1MHz... My question is if the lowest specified frequency is at F1Hz, then what phase noise characteristic do we assume for the frequency range between 0Hz to F1Hz? Shall we assume a 1/F slope from 0Hz to F1Hz? Or is it 1/F^2 slope? Or something else? Thanks! --...


Does OFDM based system use PLL or DLL for synchronization?

Started by xsong in comp.dsp8 years ago 9 replies

I have been wondering if OFDM based system use PLL or DLL as in single carrier system e.g. GSM to do synchronization at all? Currently, a lot of...

I have been wondering if OFDM based system use PLL or DLL as in single carrier system e.g. GSM to do synchronization at all? Currently, a lot of ofdm based systems talk about implementing the frequency offset and time offset compensation in the digital domain. Do they also implement the time and frequency synchronization in hardware?


PLL on TMS320C6713 to generate 1Hz output

Started by paryanz in comp.dsp11 years ago 16 replies

I am trying to implement a PLL on a board which uses the DSP TMS320C6713 floating point processor. I am planning to mount a VCXO with a freq...

I am trying to implement a PLL on a board which uses the DSP TMS320C6713 floating point processor. I am planning to mount a VCXO with a freq range of 1.5 to 77.5 Mhz range on the board. I have a reference frequency of 10 HZ and I need to generate a 1HZ freq as an output. How would you advise me to implement this on the TI DSP processor. I do understand that the output of phase detector afte...


Digital PLL acquisition problem

Started by Anonymous in comp.dsp12 years ago 14 replies
PLL

Hi all, I made a digital PLL, with multiplier based phase detector, digital loop filter C1 + C2/(1-z^-1) and a digital NCO with 16...

Hi all, I made a digital PLL, with multiplier based phase detector, digital loop filter C1 + C2/(1-z^-1) and a digital NCO with 16 bits accumulator I want to lock on a 22170 Hz sine signal in 10 ms lock time My problem is when I don't have the 22170 Hz signal, my output filter sweep very slowly (1 second) beetween min and max of my input NCO and don't lock when my 22170 Hz signal is o...


Phase detector gain for a software PLL??

Started by mir_aculous in comp.dsp8 years ago 6 replies
PLL

What will the phase detector gain for a software PLL be?

What will the phase detector gain for a software PLL be?


trig functions , coordinate conversions in Programmable DSPs

Started by ziggycal in comp.dsp13 years ago

Hi I'm looking @ implementing some algorithms (FFT , PLL ) exploiting COrdic features. Cycles are critical. Appreciate a pointer to the nest...

Hi I'm looking @ implementing some algorithms (FFT , PLL ) exploiting COrdic features. Cycles are critical. Appreciate a pointer to the nest available solution (DSP - processors that are commercially available) to achieve the same . thanks ziggycal


MIMO receiver...

Started by Anonymous in comp.dsp12 years ago 9 replies
PLL

Does a MIMO receiver have a whole analog front end for each antenna? Or can you use one PLL, ADC and Filter, and switch between the antennae?

Does a MIMO receiver have a whole analog front end for each antenna? Or can you use one PLL, ADC and Filter, and switch between the antennae?