MIMO receiver...

Started by Anonymous in comp.dsp13 years ago 9 replies
PLL

Does a MIMO receiver have a whole analog front end for each antenna? Or can you use one PLL, ADC and Filter, and switch between the antennae?

Does a MIMO receiver have a whole analog front end for each antenna? Or can you use one PLL, ADC and Filter, and switch between the antennae?


Loop Filter Modelling

Started by pruthvisri02 in comp.dsp12 years ago 6 replies

Hallo, I am relatively new to RF electronics,I need some support for modelling my blocks in PLL.The block we have problem is third...

Hallo, I am relatively new to RF electronics,I need some support for modelling my blocks in PLL.The block we have problem is third order LoopFilter (L.F). Here we go ---> The Transfer Function (T.F) for L.F -> (ds+1)/s(as**2+bs+c) we deduced the above T.F -> k1/s + k2/(s-r1)+k3(s-r2) where r1 and r2 are the roots of the quadratic equation in T.F & a,b,c,d are constants. And I reduced it to ti


TMS320LF2407 Problems

Started by J.Oscar in comp.dsp16 years ago 2 replies
PLL

Hi I am developing an motor control with TMS320LF2407. (I have a design with F240). My first prototype is nort running. I am not using internal...

Hi I am developing an motor control with TMS320LF2407. (I have a design with F240). My first prototype is nort running. I am not using internal PLL and I think DPS is not working properly. Can someone send me electrical diagram of LF2407A Evaluation module EVM. my e mail is o.alegria@montelec.net Thank you Best regards Oscar


OFDM Question

Started by Bob the Builder in comp.dsp13 years ago 4 replies

I was wondering about demodulation. We woudl need phase coherence of both the main carrier and the sub-carriers. I assume the main carrier can...

I was wondering about demodulation. We woudl need phase coherence of both the main carrier and the sub-carriers. I assume the main carrier can be locked onto with a PLL but what about the sub-carriers? Do they use a pilot sequency of some sort when multiply up to get the other frequencies? Thanks Tom


The best Free PLL simulation (to see frequency vs time behaviour)

Started by Ro_ny in comp.dsp5 years ago 4 replies
PLL

That I can connect it additional components e.g. opamps, logic gates etc... (that's why software like ADIsimPLL isn't suitable). Does LTSpice...

That I can connect it additional components e.g. opamps, logic gates etc... (that's why software like ADIsimPLL isn't suitable). Does LTSpice have a built-in VCO component that can be added, and its range can be set to any frequency for example 1.5GHz? Thanks to all who help. _____________________________ Posted through www.DSPRelated.com


PLL to generate low frequencies

Started by paryanz in comp.dsp10 years ago 12 replies
PLL

Hi, This is my first post to this forum. I have a reference oscillator of 12.7 MhZ, how do I generate the following frequencies using this...

Hi, This is my first post to this forum. I have a reference oscillator of 12.7 MhZ, how do I generate the following frequencies using this oscillator 16.863406408094434 Hz 16.722408026755854 16.694490818030051 13.755158184319120 12.562814070351759 12.531328320802006 12.062726176115802 11.148272017837234 10.405827263267431 10.060362173038229 10.040160642570282...


Would Eric Jacobsen Please Pick Up a White Courtesy Telephone

Started by Tim Wescott in comp.dsp9 years ago 7 replies
PLL

And email me. I dimly recall that someone suggested a software PLL paper, and that you were getting shoved forward as a co-author (or even...

And email me. I dimly recall that someone suggested a software PLL paper, and that you were getting shoved forward as a co-author (or even volunteering). At any rate, I'm going to see if I have time to start on this; if you're interested in working with me on this let me know. tim at wescottdesign dot com (if the spammers ever learn to read English we're doomed). -- www.wescot...


FM as "analog FEC"

Started by Tim Wescott in comp.dsp5 years ago 3 replies

One of the comments on the "VCO in a PLL" thread got me to thinking. I remember being struck by the similarity in the waterfall curves between...

One of the comments on the "VCO in a PLL" thread got me to thinking. I remember being struck by the similarity in the waterfall curves between FEC coding on the one hand, and FM radio on the other. One is in BER vs. Eb/No, and the other is in output SNR vs. input SNR, but both are showing that when you transmit a signal with redundant information you'll get improved performance up to s...


McBSP Max Speed???

Started by Anonymous in comp.dsp14 years ago 1 reply

Hi all, we are working with TI OMAP5912. We are using one of it's McBSP for i2s communication. The TI CHIP is getting 12MHz external clock...

Hi all, we are working with TI OMAP5912. We are using one of it's McBSP for i2s communication. The TI CHIP is getting 12MHz external clock and internally it's working on 200MHz using PLL. But we are not able to find out what the maximum speed these McBSP supports? anybody having experience with this please reply us. Shridhar.


Re: Software PLL (SPLL)

Started by Noway2 in comp.dsp13 years ago
PLL

Tim, That was a very nice explanation. I have always considered software PLLs to be a bit of an enigma, though a future project goal of mine...

Tim, That was a very nice explanation. I have always considered software PLLs to be a bit of an enigma, though a future project goal of mine is going to require one. In my case, the reference and the incoming signal will both be aprox 50 or 60hz sine waves. For the PFD, I was planning on multiplying them and filtering the result which would be used to drive the NCO. I was wondering i...


Re: Software PLL (SPLL)

Started by Tim Wescott in comp.dsp13 years ago
PLL

Noway2 wrote: > Tim, > > That was a very nice explanation. I have always considered software > PLLs to be a bit of an enigma, though a...

Noway2 wrote: > Tim, > > That was a very nice explanation. I have always considered software > PLLs to be a bit of an enigma, though a future project goal of mine is > going to require one. In my case, the reference and the incoming > signal will both be aprox 50 or 60hz sine waves. For the PFD, I was > planning on multiplying them and filtering the result which would be > used to driv


Better FM demodulator

Started by chris1911 in comp.dsp13 years ago 16 replies

Currently, I have a project that uses the Blackfin DSP. A 8-bit A/D will do undersampling (at 1.6384MHz) of an IF signal which is...

Currently, I have a project that uses the Blackfin DSP. A 8-bit A/D will do undersampling (at 1.6384MHz) of an IF signal which is down-converter from standard stereo FM broadcast. There are quite a few standard FM demodulators, e.g. baseband delay, phase-adapter, mixed type and PLL demodulator. It seems the mixed demodulator should have the best performance among those four. Is there any other ...


How to decrease wander in SDH

Started by fl in comp.dsp8 years ago 5 replies
PLL

Hi, On SDH signal, clock jitter can be removed by PLL. How about wander? The definition of wander is below 10 Hz. I am curious on how...

Hi, On SDH signal, clock jitter can be removed by PLL. How about wander? The definition of wander is below 10 Hz. I am curious on how to decrease it. Thanks


Derivative of signal

Started by Mimar in comp.dsp6 years ago 26 replies
PLL

Hello, could somebody give me an advice? At the moment I am solving interesting problem. I have been using SW PLL with SOGI circuit to obtain...

Hello, could somebody give me an advice? At the moment I am solving interesting problem. I have been using SW PLL with SOGI circuit to obtain grid frequency since April and I have to say I am very happy, it works very well. Accuracy is two decimal places. But my chief said me last week, we will need to measure some changes (= first derivative, signal trend) of resulting frequency soon. At first...


xr2211 & non coherent fsk demodulation

Started by josedebrest in comp.dsp12 years ago 1 reply

Hello, I am using the XR 2211 to demodulate a non coherent fsk signal. It works but I would like to know how to evaluate the theoritical...

Hello, I am using the XR 2211 to demodulate a non coherent fsk signal. It works but I would like to know how to evaluate the theoritical BER performance of this demodulation. But all the non coherent fsk receivers that are mentionned on the web dont use a pll ... any idea ? thank you very much jean michel


FM Demodulation

Started by Randy Yates in comp.dsp12 years ago 61 replies

Gentle and Wise Readers of comp.dsp, Two ways to demodulate FM are: 1. Find the instantaneous phase (e.g., by examining the phase of the ...

Gentle and Wise Readers of comp.dsp, Two ways to demodulate FM are: 1. Find the instantaneous phase (e.g., by examining the phase of the analytic signal) and compute the phase differences, i.e, f = dtheta/dt. 2. Lock a PLL to the FM signal and use the VCO control voltage as the demodulated signal. It seems to me that method 1 is much simpler. Why would anyone do FM demodulat...


200kHz to 30MHz phase detection stratergies.

Started by Anonymous in comp.dsp4 years ago 9 replies

hey guys, I am currently dealing with sinusoidal signals ranging between 200k and 30MHz and have to measure a phase difference of a few...

hey guys, I am currently dealing with sinusoidal signals ranging between 200k and 30MHz and have to measure a phase difference of a few millidegrees between the two signals. I have read up on a few stratergies like using a PLL or IQ demodulation, but since we are working with such high frequencies it is best to obtain advice from experts here. thanks very much. Best wishes Zoul


Re: Software PLL - the math that i did looks too simple to be true - please confrim

Started by Jerry Avins in comp.dsp8 years ago

On Tuesday, February 8, 2011 11:39:55 AM UTC-5, Tim Wescott wrote: ... > Robert, there's a heck of a lot more different types of phase...

On Tuesday, February 8, 2011 11:39:55 AM UTC-5, Tim Wescott wrote: ... > Robert, there's a heck of a lot more different types of phase detectors= =20 > than just multiplying the two waveforms together. Each one has its own= =20 > impact on how the loop behaves, some making it easier to design the=20 > loop, some harder. So far you seem stuck on the "phase detector=20 > multiplies s


phase lock loop(PLL) help

Started by biras in comp.dsp14 years ago 1 reply
PLL

hi i need help to design the loop filter for phase lock loop ic (4046).my input frequency is 40 t0 70 HZ AND my VCOout frequency is 256 to...

hi i need help to design the loop filter for phase lock loop ic (4046).my input frequency is 40 t0 70 HZ AND my VCOout frequency is 256 to 448 KHZ.my VCC IS 5 Volt thank you R.birasanna


phase lock loop(PLL) help

Started by biras in comp.dsp14 years ago 4 replies
PLL

hi i need help to design the loop filter for phase lock loop ic (4046).my input frequency is 40 t0 70 HZ AND my VCOout frequency is 256 to...

hi i need help to design the loop filter for phase lock loop ic (4046).my input frequency is 40 t0 70 HZ AND my VCOout frequency is 256 to 448 KHZ.my VCC IS 5 Volt thank you R.birasanna