Digital FM Demodulation

Started by Jon in comp.dsp15 years ago 3 replies

Hi all, After seaching the comp.dsp archive for FM demod I did not find anything on the case where there is a frequency offset between...

Hi all, After seaching the comp.dsp archive for FM demod I did not find anything on the case where there is a frequency offset between the transmitter and receiver. Is there a reference that explains how the frequency offset between the transmitter and reciever effects the performace of the demodulator? I assume that a digital PLL implementation would be required or would the method in t...


MASH 1-1 sigma delta modulator

Started by adani in comp.dsp12 years ago 2 replies
PLL

hi all, can somebody share the pseudo-code of MASH 1-1 sigma delta modulator for fractional-N pll. Thanks adani

hi all, can somebody share the pseudo-code of MASH 1-1 sigma delta modulator for fractional-N pll. Thanks adani


Re: Software PLL (SPLL)

Started by Tim Wescott in comp.dsp13 years ago

kirgizz wrote: > Hello board, > > I'm dealing with synchronisation issue and looking for a cheap solution > for my design. > > ...

kirgizz wrote: > Hello board, > > I'm dealing with synchronisation issue and looking for a cheap solution > for my design. > > > Firstly, my external reference frequency is variable and can change, for > example, in sweep mode (5Hz per sec). Secondly, the exact information > about > the ext. reference frequency is used for internal calculations in DSP (to > generate frequency-lock


PLL resolution

Started by Grant in comp.dsp11 years ago 9 replies

Is there a limit to achievable resolution of a phase-locked loop given no noise and arbitrary acquisition time? If so, what is that...

Is there a limit to achievable resolution of a phase-locked loop given no noise and arbitrary acquisition time? If so, what is that limit? For example, is 0.1 degree phase resolution of a 10 kHz sinusoid reasonably achievable in practice if we assume > 60 dB S/N, no frequency error and tens of seconds to acquire? Thanks.


Another Eb/No Question

Started by Necronomicon in comp.dsp11 years ago 13 replies

Does Eb/No, as used in digital communication calculations for signal to noise ratios, take into account the VCO/PLL/Reference phase noise of the...

Does Eb/No, as used in digital communication calculations for signal to noise ratios, take into account the VCO/PLL/Reference phase noise of the carrier(s)? I ask because the phase noise is never really flat, and the Noise Power Spectral Density, or "No", is in Watts/Hz, which is assuming that the noise is flat across all frequencies (white noise). Certainly one could use the integrated ...


Software PLL (SPLL)

Started by kirgizz in comp.dsp13 years ago 4 replies

Hello board, I'm dealing with synchronisation issue and looking for a cheap solution for my design. Firstly, my external reference...

Hello board, I'm dealing with synchronisation issue and looking for a cheap solution for my design. Firstly, my external reference frequency is variable and can change, for example, in sweep mode (5Hz per sec). Secondly, the exact information about the ext. reference frequency is used for internal calculations in DSP (to generate frequency-locked inphase and quadrature sine waves). T...


Manchester decoding (BPSK), variable frequency

Started by jneudorf in comp.dsp9 years ago 5 replies

Hi all. Need to figure out the best way to decode 1200bps Manchester data words sent according to the DALI protocol (IEC 60929 or its...

Hi all. Need to figure out the best way to decode 1200bps Manchester data words sent according to the DALI protocol (IEC 60929 or its newer replacement) on a small micro. One issue is that the bit rate can vary by as much as +/- 10% (1091bps - 1391bps); I suspect that a PLL won't be able to synchronize quickly enough to avoid data loss, especially since the phase of the clock can change between ...


Re: What's the use of a 192 kHz sample rate?

Started by Piergiorgio Sartor in comp.dsp11 years ago 2 replies

Mr.T wrote: > No, the *input* rate is changed by varying the speed of the disk motor. Yes, that's the close part of the PLL and it...

Mr.T wrote: > No, the *input* rate is changed by varying the speed of the disk motor. Yes, that's the close part of the PLL and it is where the problem lies, since the motor cannot, or is not designed for, change speed immediately. It has a momentum, friction, and so on. Due to cost reasons, it does not react in zero time to the changes, also because of the disk (balance, weight, again


Spectral line for timing recovery

Started by commsignal in comp.dsp6 years ago 9 replies
PLL

Hi, As we know, any non-linearity on matched filter output contians two spectral lines at +/- symbol rate. I am a little confused about how to...

Hi, As we know, any non-linearity on matched filter output contians two spectral lines at +/- symbol rate. I am a little confused about how to use that for timing compensation. If it is used as a TED for a PLL, will not the loop filter reject this line? Secondly, coming to the time domain, is the top of this sinusoid refers to the ideal timing phase? Thanks.


coherent sampling and I/Q demod

Started by petethepop in comp.dsp14 years ago 1 reply

(how) does coherent sampling (used primarily in A/D testing?) differ from I/Q demodulation? Say for instance I'm using I/Q to close a PLL. In...

(how) does coherent sampling (used primarily in A/D testing?) differ from I/Q demodulation? Say for instance I'm using I/Q to close a PLL. In this case the 'sine wave' I'm locked to is being sampled at x4 the sine frequency. This would seem to satisfy the coherent sampling requirement that regarding the digitizer clock. next question - coherent sampling removes the need for windowing in FFT ap...


Re: Software PLL (SPLL)

Started by Ron N. in comp.dsp13 years ago

Dougal McDougal of that Elk wrote: > You need to watch the stability - ie phase margin. Make sure you sample at > about ten times the unity...

Dougal McDougal of that Elk wrote: > You need to watch the stability - ie phase margin. Make sure you sample at > about ten times the unity gain cross-over freq. Your unity gain freq could > be around 12Hz - this should filter out the 2f at 120Hz. You may also need a > phase-lead compensator depending on the number of integrators you want (ie > for just the VCO you have one integrator - but


Electronic Guitar Tuners

Started by rickman in comp.dsp6 years ago 54 replies

I am being asked to design a gadget that has some special features, but also includes a guitar tuner. I have looked at the web a bit, but not...

I am being asked to design a gadget that has some special features, but also includes a guitar tuner. I have looked at the web a bit, but not found any good references that show exactly how a tuner works. One paper I found talked about a rather complex "constant Q transform". I just don't think the $10 tuner I have uses anything that complex. I'm thinking they are doing a PLL sync to...


Demodulator Timing Recovery Architecture Question

Started by Randy Yates in comp.dsp13 years ago 12 replies

Which would be a better architecture: using a hardware VCO to drive the ADC as part of the PLL for timing recovery, or using a fixed-crystal...

Which would be a better architecture: using a hardware VCO to drive the ADC as part of the PLL for timing recovery, or using a fixed-crystal oscillator for the ADC and resampling in the digital domain? Assume the latter is done on a processor and not in hardware. -- % Randy Yates % "Watching all the days go by... %% Fuquay-Varina, NC % Who are you and who ...


Rulph Chassaing's DSP Application Using C and the TMS320C6x DSK

Started by Wildcardz in comp.dsp14 years ago 3 replies
PLL

I am a hobbiest and have a copy of Rulph Chassaing's book on DSP Applications Using C. There is a chapter on student projects, and I found the...

I am a hobbiest and have a copy of Rulph Chassaing's book on DSP Applications Using C. There is a chapter on student projects, and I found the source code for a PLL project on the accompanying CD. However, the designstep.m file appear to call some other functions tf, tfdata, c2d, and zpkdata. Anyone know where I can find errata or updates to the book? Thanks. PS: I just learnt of Dr. Ch...


Carrier Recovery for QPSK

Started by Ali A Nasir in comp.dsp9 years ago 1 reply

Hi everyone, As a part of problem, I have to implement carrier recovery in some distributed MISO communication system. I was following one...

Hi everyone, As a part of problem, I have to implement carrier recovery in some distributed MISO communication system. I was following one paper to implement that problem which targeted to estimate the f offset in the range of (1 / (2Ts) ) ( for Ts is the oversampling time ). The f offset is estimated with minute error about which author suggested the use of PLL to handle it, but didn't r...


Costas loop parameters

Started by Anonymous in comp.dsp12 years ago
PLL

Hi, I would like to design a Costas Loop I have a loop filter : F(s) = (tau2.s+1) / (tau1.s) so i have the resonant frequency at : wn =...

Hi, I would like to design a Costas Loop I have a loop filter : F(s) = (tau2.s+1) / (tau1.s) so i have the resonant frequency at : wn = sqrt (Kd.Ko / tau1) Kd : is the phase comparator gain (V/rd) Ko : is the VCO gain : (rad/s/V) and the damping factor : z = 0.5 * tau2 * wn Is the settling time is like a second order PLL to be : wn * Ts(5%) = 3 for a z = 0.707 ? Because when I c...


Phase-frequency detector with synchronous output?

Started by Chris Maryan in comp.dsp9 years ago 5 replies

I'm looking at ways of implementing a PLL (minus the VCXO) entirely in an FPGA. Our traditional approach has been to have PFD in the FPGA, take...

I'm looking at ways of implementing a PLL (minus the VCXO) entirely in an FPGA. Our traditional approach has been to have PFD in the FPGA, take the up/down pulses and run them into an external charge pump- > filter-> VCXO. I would like to move everything up to the VCXO inside the FPGA (naturally there ould be a D-A involved to drive the external VCXO). The particular part of this problem tha


RTTY (AFSK) demodulation

Started by sven98de in comp.dsp9 years ago 14 replies

Hi, has somebody here implemented a RTTY (AFSK) decoder. Any suggestions how to proceed ? I've found some technical abstracts about FSK...

Hi, has somebody here implemented a RTTY (AFSK) decoder. Any suggestions how to proceed ? I've found some technical abstracts about FSK demodulation in the WEB like: - frequency discriminator with IIR resonator - frequency discriminator with FIR bandpass filter - digital PLL Any idea how complex it is to implement one of these methods ? What processor is sufficient for this, does a microc...


Replacement for Ubicom IP2022 => C5509a? what others could i use?

Started by Anonymous in comp.dsp10 years ago
PLL

Hi, The company I just started working for has tasked me to find a suitable replacement for the current mcu (IP2022) The specific...

Hi, The company I just started working for has tasked me to find a suitable replacement for the current mcu (IP2022) The specific characteristics that are needed are: - Fast wakeup time ( less than 300us for wake from pll stop to first instruction crunched) - Low current in standby (less than 200uA) - greater than 120MIPs - preferably 2 channel DMA (frees up a heck of a lot of cp...


Low SNR BPSK clock synch

Started by john in comp.dsp14 years ago 3 replies
PLL

All, I'm curious about practical implementations of very low SNR clock synchronization for non-burst coherent BPSK. I have been doing...

All, I'm curious about practical implementations of very low SNR clock synchronization for non-burst coherent BPSK. I have been doing some work in this area, and have found that a nonlinearity, narrow BPF, and 2nd order transition tracking PLL works quite well to 20% SER and beyond. Some of my colleagues don't believe it, pointing to papers that claim MAP detectors fail well before that po...