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effect of clock jitter on ADC

Started by praveen in comp.dsp20 years ago 2 replies

Hello, I am designed a DSP based which measures the rotation rate (sagnac phase). But the problem i am facing is that jitter in the clock...

Hello, I am designed a DSP based which measures the rotation rate (sagnac phase). But the problem i am facing is that jitter in the clock which is used as sampling input to the ADC will spoil by algorithm. The sampling point is very crucial. How can i solved this problem. suggest we a solution waiting for reply with regards praveen


Effective realization of the filter with an abrupt transitive strip?

Started by alex65111 in comp.dsp16 years ago 7 replies

It is necessary to solve a following problem. Frequency of sampling ? 120kH. It is necessary to calculate and realize the low-frequency...

It is necessary to solve a following problem. Frequency of sampling ? 120kH. It is necessary to calculate and realize the low-frequency filter with a passband 29 kH, frequency of stopband 30 kH, ripple in a passband no more 0,1dB, suppression not less 96dB, the phase should be linear. After a filtration a signal decimated twice, up to frequency of sampling 60 kH. What approaches can be for t


Basic Sub-Nyquist Sampling

Started by Craig in comp.dsp21 years ago 2 replies

I am having some difficulty understanding the sub-nyquist sampling theory. For example: if you have an ADC that can only operate at 250MHz,...

I am having some difficulty understanding the sub-nyquist sampling theory. For example: if you have an ADC that can only operate at 250MHz, then the max bandwidth is 125MHz. However, if I wanted 1000MHz and I want to use the same ADC, the bandwidth would "fold" into 125MHz output band. So I could potentially have 8 solutions if I injected in a 40MHz signal. 40, 210, 290, 460, 540, 710...


Data Acquisition

Started by rogerdff in comp.dsp16 years ago 3 replies

Dear all, I have to develop an application with the following basic requirements: - 40 analog channels of Voltage/Current - ADC with 16 bits...

Dear all, I have to develop an application with the following basic requirements: - 40 analog channels of Voltage/Current - ADC with 16 bits of resolution - at least 96 sample point per cycle (50 and 60Hz), which means 4800 and 5760Hz of sampling frequency - simultaneous sampling of all channels The main concern is data acquisition. It is a like a data logger. Since a lot of mat...


Sampling theorem, Christensen, frame theory and so on

Started by st256 in comp.dsp13 years ago 1 reply

As I know Ole Christensen proved correctly the Sampling Theorem using the Frame Theory. Could you provide me with a reference to this proof?

As I know Ole Christensen proved correctly the Sampling Theorem using the Frame Theory. Could you provide me with a reference to this proof?


signal detection in doppler

Started by cpshah99 in comp.dsp16 years ago 12 replies

Hello People I have been scratching my head on this doppler problem: Because of the doppler effect, the received signal will either be...

Hello People I have been scratching my head on this doppler problem: Because of the doppler effect, the received signal will either be expanded or compressed on time axis. Now, the expansion or compression is sampling rate conversion. So, I tried to use 'resample' function of matlab. The actual length of the signal is 30720 and sampling freq is 48000Hz. Now, when I use y=resample(x,100...


Adjustment of parameters of function rcosine?

Started by alex65111 in comp.dsp16 years ago

Endurance from Matlab help (num = rcosine(Fd,Fs) designs a finite impulse response (FIR) raised cosine filter and returns its transfer...

Endurance from Matlab help (num = rcosine(Fd,Fs) designs a finite impulse response (FIR) raised cosine filter and returns its transfer function. The digital input signal has sampling frequency Fd. The sampling frequency for the filter is Fs. The ratio Fs/Fd must be a positive integer greater than 1. ) 1. What is Fs?, why Fs/Fd should be the whole? 2. What is delay? 3. By what criteria it ...


Interpolated frequency sampling linear-phase FIR design

Started by Andor in comp.dsp19 years ago 8 replies

Friends, I face the following problem. Because several vectors of differing lenghts occur in the description, I use Harris' convention of...

Friends, I face the following problem. Because several vectors of differing lenghts occur in the description, I use Harris' convention of writing [h(n):M] to denote the vector h of length M. Assume I specify the desired magnitude response of a linear-phase FIR filter at N/2+1 evenly spaced points [H(n):N/2+1], starting with 0, ending at Fs/2, where Fs is the sampling rate. Then use the i...


Anti-Aliasing filter

Started by naebad in comp.dsp19 years ago 21 replies

Ok I am sampling with an ordinary A/D (not sigma-delta) at 11025kHz which mean I need any noise to be attenuated at half sampling which is at...

Ok I am sampling with an ordinary A/D (not sigma-delta) at 11025kHz which mean I need any noise to be attenuated at half sampling which is at 5512.5Hz. I have read that the nosie level needs to be less that the R.M.S Quantisation Level of my A/D. Now I swing +or - 10 volts with 16 bits. So my Quantisation level is delta = dynamic range/2^16=20/65536=0.000305176 volts. (or 0.305mV) Now...


Multiple ADCs and aliasing

Started by Piotr Wyderski in comp.dsp6 years ago 71 replies

I have two 1MHz ADCs and would like to interleave them by a half of the sampling cycle in order to get a single ADC with effective sampling...

I have two 1MHz ADCs and would like to interleave them by a half of the sampling cycle in order to get a single ADC with effective sampling frequency of 2MHz (I want to oversample the signal by as much as possible). But the aliasing properties of the data stream will be as if the signal was sampled at 1MHz because the ADCs are independent blocks and don't influence each other, right? Bes...


Sampling Frequency effect on OFDM

Started by OFDMnewuser in comp.dsp10 years ago 1 reply

Hi, I am doing a baseband simulation for IEEE 802.11 g. The standard uses 64 IFFT length (3.2?s) and 20 Msamples per second. I think this result...

Hi, I am doing a baseband simulation for IEEE 802.11 g. The standard uses 64 IFFT length (3.2?s) and 20 Msamples per second. I think this result in one sample per symbol. I am wondering what the structure will be if I use 40 Msample per second, i.e will the IFFT size change, or interpolation will be used? or what is the effect of sampling frequency on the baseband simulation? Best Regards,


Dithering for

Started by Yazz in comp.dsp17 years ago 37 replies

Hopefully some of you guru's here can set me straight here. In an attempt to reduce quantization spurs, I have read about dithering. I have...

Hopefully some of you guru's here can set me straight here. In an attempt to reduce quantization spurs, I have read about dithering. I have seen wideband dithering and narrowband dithering. All of this is done in the analog domain prior to the sampling. My question is: Why can we not simply add a random LSB (+/- 1) to each of the samples AFTER sampling to reduce quantization spurs ? ...


Oversampling vs. nr. Bits

Started by galatisa in comp.dsp19 years ago 3 replies

Hi, I'm sampling a signal with a 35 MHz BW at a rate of 100Msa/s and 12 bit. The nature of the signal is something like 100ns Peaks at about 2/3...

Hi, I'm sampling a signal with a 35 MHz BW at a rate of 100Msa/s and 12 bit. The nature of the signal is something like 100ns Peaks at about 2/3 of peak value. I need the integration over each signal(100ns) but due to the sampling rate I only get at about 4-10 samples of every signal, a number which is not enough. So I thougth of oversampling but since the data stream is processed by a virte...


Sample rate estimation using a PLL?

Started by snappy in comp.dsp19 years ago 3 replies

Hello DSP:ers, I have a delicate problem: two audio devices, not synchronized by any means, are set to the same sampling rate. In reality the...

Hello DSP:ers, I have a delicate problem: two audio devices, not synchronized by any means, are set to the same sampling rate. In reality the sampling rates will differ a little bit, i.e. 44000 and 44001 Hz. Now I need a way of estimating the clock drift between those two devices, preferably in real time: One device is the playback device, and the other one is the recording device (recordi...


Cut-off frequency and sampling frequency IIR filter

Started by Anonymous in comp.dsp17 years ago 2 replies

Hi all, I have a little question... Is there a trade-off beetween the cut-off frequency of an IIR filter and it's sampling frequency...

Hi all, I have a little question... Is there a trade-off beetween the cut-off frequency of an IIR filter and it's sampling frequency ? In practice I have noticed that we cannot have a relation more than Fs = 100 * Fc with 16 bits coeffcients... Is there a theoritical proof ? Thanks


Question about spectrum analysis and sampling theory

Started by Krellan in comp.dsp13 years ago 15 replies

This is probably a FAQ, but I looked for a while and couldn't find an answer. Apologies in advance. What is the "sweet spot" in a spectrum...

This is probably a FAQ, but I looked for a while and couldn't find an answer. Apologies in advance. What is the "sweet spot" in a spectrum analysis waterfall display, for generating or decoding a narrower signal that's embedded within it? Let's say I'm sampling at 48 kHz, and there's a signal in there that's 10 kHz wide. Where shall I place this signal? If it's too far left (lower fr...


FFT and estimating frequencies not on discrete points

Started by Anonymous in comp.dsp16 years ago 13 replies

Assume there is a real function f and its spectrum F. If f is discrete sampled, we have samples at some t = st * k, where st is sampling period...

Assume there is a real function f and its spectrum F. If f is discrete sampled, we have samples at some t = st * k, where st is sampling period and k = 0, 1, 2, ..., N - 1. Also assume every frequency in f is within [-fc..fc] range, fc = Nyqist frequency. If f is a simple sine function whose minimums, zeros and maximums are at the sampling points, F will be very "good", without leakage and ju...


Sampling frequency requirements

Started by Allan Wilson in comp.dsp20 years ago 7 replies

Hi, I've got a sampling frequency question. I have two signals, which only have frequency components up to about 100Hz, from two sensors in...

Hi, I've got a sampling frequency question. I have two signals, which only have frequency components up to about 100Hz, from two sensors in a liquid stream. I need to get the phase (time) difference between these two signals with a resolution of 0.2ms to be able to calculate the velocity of the liquid to the accuracy required. Note the velocity of the liquid is continuously variable and ...


Frequency Analysis parameters

Started by Matti Lamprhey in comp.dsp20 years ago 8 replies

What are the parameters which are required to completely specify the frequency analysis of an audio stream? I'm assuming they are roughly as...

What are the parameters which are required to completely specify the frequency analysis of an audio stream? I'm assuming they are roughly as follows: 1. incoming sampling rate 2. incoming sampling bitlength 3. floor frequency 4. ceiling frequency 5. number of bins 6. no of samples per frame 7. sample displacement between frames (overlap) Thanks, Matti


Looking for ~100MSs 2 channels DAQ board, 70MHz IF, ...

Started by christophe grimault in comp.dsp20 years ago 2 replies

Hi, I'm looking for a DAQ (digitizing board) on PCI, with 2 (or 4) channels. The sampling rate should be around 100 MS/s max with a least 50...

Hi, I'm looking for a DAQ (digitizing board) on PCI, with 2 (or 4) channels. The sampling rate should be around 100 MS/s max with a least 50 MHz bandpass. The board shall have tens to hundreds of Mb of RAM to acquire a few seconds of signal in one shot. Then download to a PC for further processing. The input shall be at IF of 70 MHz and the board shall do preferably IQ sampling. A pl...