Digital filters FPGA implementation

Started by grigoriou_i in DSP & FPGA10 years ago 1 reply

Greetings, I have selected this topic for my dissertation topic and, since I have more of an Informatics background, I need some guidance. My...

Greetings, I have selected this topic for my dissertation topic and, since I have more of an Informatics background, I need some guidance. My only experience with FPGAs so far is with Celoxica's RC10 board, where I implemented the Haar Discrete Wavelet Transform algorithm using Handel-C. I've made a little research and found these books: 1) Lyons, Understanding Digital Signal Processing 2)...


Inverse FFT Results

Started by norw...@yahoo.com in DSP & FPGA10 years ago

I will do my best to explain my problem clearly. I have this same problem using Labview, Matlab, and Scilab. I start by building an array...

I will do my best to explain my problem clearly. I have this same problem using Labview, Matlab, and Scilab. I start by building an array with three frequencies (f1,f2,and f3) starting at different times. f1 for .5 seconds, f2 for .25 seconds, and f3 for .25 seconds. So, I have one second worth of data consisting of three frequencies that are at different times. Then, I do an FFT of th...


Narrow band FIR filter

Started by rama...@gmail.com in DSP & FPGA10 years ago 2 replies

hi, I am looking for Hardware/FPGA friendly FIR filter design. The sampling rate is around 1250 MHz. FIR filter should be tunable with pass...

hi, I am looking for Hardware/FPGA friendly FIR filter design. The sampling rate is around 1250 MHz. FIR filter should be tunable with pass band of 5 MHz and cut-off of 2.5MHz on both sides. I plan to design a low pass filter of 2.5MHz pass band and cut-off at 2.5MHZ, with attenuation becoming zero by 5MHz. This i plan shift to various frequencies my multiplying co-efficients to make it tun...


Undersampling

Started by meht...@gmail.com in DSP & FPGA10 years ago 2 replies

I am amature to Software Defined Radios. I am facing a problem regarding the selection of sampling frequency of ADC. How to decide the sampling...

I am amature to Software Defined Radios. I am facing a problem regarding the selection of sampling frequency of ADC. How to decide the sampling frequency so the carriers of different channels do not overlap. I want to tune the receivers to different FM channels. These are the different frequencies to which I want to tune the receiver. Radio Mirchi 98.3 FM Radio City 91.1 FM R...


Signal communication betweem process in VHDL

Started by bing...@meidensg.com.sg in DSP & FPGA11 years ago 1 reply

Hi, I found a strange problem. In the following VHDL code, I want to use a signal named (coming) to tell another process data is coming. But I...

Hi, I found a strange problem. In the following VHDL code, I want to use a signal named (coming) to tell another process data is coming. But I found it did not work. And if I delete all the case portion in the second process, it works. Why? Could anyone give me a hint? Thanks entity filter is port(indata:in std_logic_vector(7 downto 0); outdata:out std_logic_vector(rank-1 downto 0);...


Need help with Power estimation for a Xilinx Virtex5 FPGA

Started by Ishita Dalal in DSP & FPGA11 years ago 1 reply

Hello everyone,I am currently working on a thesis project. As a part of my project, I have developed several design architectures to implement a...

Hello everyone,I am currently working on a thesis project. As a part of my project, I have developed several design architectures to implement a high speed, memory intensive DSP algorithm (Discrete Wavelet Transform). As a part of my thesis I have to compare the performance results of these designs with respect to area,clock and power. I have already synthesized my designs on the Virtex 5 (XC5VSX5...


High performance matrix multiplication hardware

Started by Victor Suarez in DSP & FPGA11 years ago 1 reply

Hi. I need to develop a hardware for hi-performance matrix-to-vector multiplications. Say, a hardware that calculates y = Ax Being x and...

Hi. I need to develop a hardware for hi-performance matrix-to-vector multiplications. Say, a hardware that calculates y = Ax Being x and y vectors and A a matrix. Vectors have a few thousand elements and A is a rectangular matrix of n*m elements, being n and m about a few thousand elements. Element data types are 16bit but it's needed an accumulator of about 48-bit. Variable x changes ...


Simulink DSP Tools

Started by eyal...@baesystems.com in DSP & FPGA11 years ago 1 reply

I'm curious as to what the general attitude of the community towards various Simulink/FPGA DSP tools is. I am aware of four different existing...

I'm curious as to what the general attitude of the community towards various Simulink/FPGA DSP tools is. I am aware of four different existing tools for converting Matlab Simulink models to FPGA code: Xilinx System Generator Altera DSPbuilder Synplicity's SynDSP Simulink's variant (Name escpaes me) I am a heavy user of Xilinx System Generator, and think it significantly cuts developmen...


What is the secret of upsampling by 4???

Started by ytac...@ou.edu in DSP & FPGA11 years ago

Hello, During my readings in DSP for SDR applications using FPGA, I found an interesting note which is the upsampling ratio of 4. I found this...

Hello, During my readings in DSP for SDR applications using FPGA, I found an interesting note which is the upsampling ratio of 4. I found this in two different locations, one at digitizing the IF signal and one at upsampling before pulse shaping. My question is about the reasons of choosing the ratio of 4 for these two cases. I am elaborating on them in the text below: 1- For IF sampling at ...


IIR filter in VHDL

Started by "kamran.wadood" in DSP & FPGA11 years ago 2 replies

Hi there, I am implementing an IIR filter in VHDL/FPGA. I've done it in MATLAB/SIMULINK as a starting point in 2 ways: 1. using FDA tool 2....

Hi there, I am implementing an IIR filter in VHDL/FPGA. I've done it in MATLAB/SIMULINK as a starting point in 2 ways: 1. using FDA tool 2. using cannonic diagram (putting in coefficient values) Now, am trying to implement this number 2. implementing the cannonic diagram in VHDL which has got some delay elements and the multiplication/addition of these elements together with filter c...


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