Hi,
I have checked. the first input sample is fed in when index for xn
is 3. I have followed the timing.
But i found something further. The problem is due to the FFT
result.
Did you do this the last time?
1) generate 24 bit number
2) feed into the FFT
3) the 34 bit result which you obtain in VHDL testbench is piped into
a text file. afterward, you IFFT the result in matlab
the waveform you get in (3) is generated against the initial
generated waveform fed into FFT described in step (1). in addition, i
found the waveform generated here is also as described in the previous
email with the leading 7 sampes roughly the same value.
also, the final waveform for both real and complex portions is one
time sample delayed to the original input sample.
possibly that this is due to quantization errors?
thanks again.
Chris
On Jul 25, 11:53�am, Tom <tom.der...@gmail.com> wrote:
> On Jul 25, 9:49�am, chrisde...@gmail.com wrote:
>
> > 2) I run my testbench in modelsim (simulation). the testbench reads in
> > the text file of complex waveforms generated in (1). It is then fed
> > through the xilinx core generated FFT. This generates an FFT result.
> > (I have verified this output in matlab. It seems to be working fine.)
>
> Are you sure that you have got the correct timing between the first
> input data word and the other FFT core control inputs?
> For example, you have to assert the Start input a few cycles before
> you put the first data word on the input data bus of the core. Have a
> careful look at the timing diagram for pipelined streaming mode in the
> Xilinx FFT data sheet to make sure you have the timing correct in your
> simulation.
> I have used this core in almost the same configuration you describe
> with no problems.
>
> -T