On Aug 14, 11:31&#4294967295;am, "schadenfreud" <hitul.s...@gmail.com> wrote:

> I would appreciate if someone could help me by advising me on the
> implementation of a polyphase FFT filter bank on a FPGA.

<snip>

> What I'm not sure about is in order to obtain D number of bins
> (corresponding D spectral channels), whether I need to take a D-point FFT
> after summing up the polyphase FIR sub-filters or do I need to multiplex
> the sub-filters and take a D-point FFT D number of times for each
> h(i)*x(nD-i) i.e. subfilter.

To build an filter bank for demultiplexing an FDM datastream, first do
the polyphase filter, then the FFT. To combine separate channels into
an FDM stream, do an inverse FFT, then the polyphase filter. fred
harris' book "Multirate Signal Processing for Communications Systems"
is a great place to learn more about this. Also try googling for
'Transmultiplexer', 'FDM TDM', 'channelizer', etc. One paper I found
with details is here:

http://www.google.com/url?sa=t&ct=res&cd=10&url=http%3A%2F%2Fwww.telfor.org.yu%2Ftelfor2004%2Fradovi%2FSPS-5-28.PDF&ei=s3WtSOT2PJXkedjh6IUO&usg=AFQjCNEqbtzf2CUIC7aQ3d66iUR-a3HvKw&sig2=Tw4qq4THlbKZ73HKDdrGhA

Eric

>If I'm following you correctly, you want to use the output of the
polyphase
>legs as the input to the FFT (ie with D legs, you use a D-pt FFT). 
Don't
>FFT an individual leg, and don't add the legs and FFT that.  I could be
>wrong however.  Check out Fred Harris's multirate DSP book for more
info.
>

Hi Impoliticus,

Thanks for your reply.

Unfortunately, I don't have access to the book that you recommend.

From what I've understood, Polyphase FFT filter banks are a more stringent
variant of Weighted Overlap & Add (WOLA). 
I was just wanting to clarify that in the Polyphase FFT filter bank, do we
overlap and add the outputs of each 1/M polyphase subfilter before taking
the M point FFT?

I would appreciate any suggestions on this

Thanks 

If I'm following you correctly, you want to use the output of the polyphase
legs as the input to the FFT (ie with D legs, you use a D-pt FFT).  Don't
FFT an individual leg, and don't add the legs and FFT that.  I could be
wrong however.  Check out Fred Harris's multirate DSP book for more info.

Hi, I would appreciate if someone would be able to advise/point me on the
following 2 implementations for a decimation by M Polyphase filter bank.

Implementation 1 - I take a M point FFT on the output of each polyphase
subfilter to obtain each channel.

Implementation 2 - I add the outputs of all the polyphase subfilters and
then take a M point FFT to obtain M channels.

Would the 2 implementations vary with an variation in M?

I'm interested in finding out what the most computationally efficient
implementation is on an FPGA and so this question stems from that. If
implementation 2 is permissible then this leads to a faster computation as
the subfilter outputs don't have to be multiplexed with a FFT (provided
that 1 FFT is to be common for all sub-filters).

Thanks in advance 


>Hi,
>I would appreciate if someone could help me by advising me on the
>implementation of a polyphase FFT filter bank on a FPGA. 
>
>I understand the basic fundamentals & computationally-efficient/improved
>side-lobe rejection advantages of polyphase fft filter banks. My
>implementation is based on a polyphase decimation by D FIR filter and
the
>end application is to split the input ADC samples into 'D' channels.
>
>As far as I understand, the output of a polyphase FIR filter (i.e. y(n)
)
>
>is obtained by summing the sub-filters 
>i.e. y(n) = Summation [h(i)*x(nD-i)]
>	     i=0 to D
>
>What I'm not sure about is in order to obtain D number of bins
>(corresponding D spectral channels), whether I need to take a D-point
FFT
>after summing up the polyphase FIR sub-filters or do I need to multiplex
>the sub-filters and take a D-point FFT D number of times for each
>h(i)*x(nD-i) i.e. subfilter. I'm currently only interested in the real
FFT
>outputs and so the complex outputs can be ignored.
>
>Any advise/help on this would be highly appreciated.
>
>Thanks in advance
>
>
>

Hi,
I would appreciate if someone could help me by advising me on the
implementation of a polyphase FFT filter bank on a FPGA. 

I understand the basic fundamentals & computationally-efficient/improved
side-lobe rejection advantages of polyphase fft filter banks. My
implementation is based on a polyphase decimation by D FIR filter and the
end application is to split the input ADC samples into 'D' channels.

As far as I understand, the output of a polyphase FIR filter (i.e. y(n) )

is obtained by summing the sub-filters 
i.e. y(n) = Summation [h(i)*x(nD-i)]
	     i=0 to D

What I'm not sure about is in order to obtain D number of bins
(corresponding D spectral channels), whether I need to take a D-point FFT
after summing up the polyphase FIR sub-filters or do I need to multiplex
the sub-filters and take a D-point FFT D number of times for each
h(i)*x(nD-i) i.e. subfilter. I'm currently only interested in the real FFT
outputs and so the complex outputs can be ignored.

Any advise/help on this would be highly appreciated.

Thanks in advance