Reply by Keith E. Larson September 27, 20022002-09-27
Hi Bill

This sounds like a fairly simple board,

When you said 'bus supervisor' did you mean a *power* bus supervisor circuit
like those contained in the 775xx series of LDO's? If yes, then you could
be experiencing something similar to the problems I have run into.

In the data sheet for the LDO you will notice some graphs showing where the
LDO is stable. Though I dont know exactly what is inside these LDO's, to me
they dont seem to act like a simple op-amp style feedback. Instead they
almost seem to have a hysterisis where they dont want to turn on fast when
they have been at low idle current. Basicaly what happens if you dont have
a large enough Cout is that the output will droop (I=C*dV/dT) fast enough to
be caught by the 'bad power' detect pulsing the init. They also seem to be
sensitive to local high frequency resistance and inductance when you dont
have a local input/output capacitor (the bulk caps can be anywhere).

The other problem I had was my own fault in picking inline 100 ohm current
limit resistors for a printer port circuit (VC33 DSK prototype) that were
simply too small. When all 8 lines were in conflict the LDO did exactly
what it should and pulsed the reset shutting down the board. The problem
was that this only happened once in a blue moon (it took me a week to dig
out this now obvious problem)! So it might be worth your time to consider
if you might have some driver-driver conflicts.

The next thing I would do is check a bare board to make sure you have not
missed a VCC or Ground. Measuring power and ground around the periphary
after the chip is installed wont work since these pins are all tied together
internaly within the VC33's pad rings.

Finaly you mentioned /HOLDA (output) is floating, but you did not mention
/HOLD (input)

Hope this helps,
Keith Larson
=====================================================
All,
We have two target boards (one in-house developed and one COTS Spectrum
Digital EZDSP) for the TMS320VC33. The emulator and code composer work fine
w/ the EZDSP; however we run into problems on our target board.

System
TMS320VC33 -120 running in CLKMD0/1 => 11 (ie x5) PLL w/ 11.4 MHz crystal

4Mb Flash (x8 configuration) page1

CPLD attached to lower 8 bits of data bus and lower 4 addr bus page3

TI Bus supervisor chips one for 3.3 & one for 1.8 (cascaded per data sheet)

JTAG connected directly to processor w/ 4.74K Ohm pull ups on TMS, TDI, EMU0
& EMU1, 10K Ohm pull down on TRST, TCK tied to TCK_RET, connector is < 0.5
inches from VC33 jtag pin side.

Board has w/ 2 split power planes (3.3/1.8 under VC33), 1 GND, 2 signal, no
active signals under signals from JTAG & VC33.

Symptoms
Code composer comes up and can run simple program loaded at 0x800000 that
toggles XF0, which isn't attached to anything. XF0 toggles on the scope so
we know that the program is running. If you hit stop then the emulator
stops and as long as you don't have a disassembly window open it can be
restarted or CPU status registers or memory window can be paged through. If
a disassembly window is open then the JTAG appears to time out (no messages
are displayed other than the disassembly window contains 0x00000BAD for all
addresses starting at 0x0800000). The emulator responds appropriately to
DSP Reset and "acts" normally afterward (except for displaying disassembly
window after running).

The same sequence using the EZDSP works flawlessly.

We have verified that RESET is high, the clock is stable, SHZ is high,
Edgemode is grounded, MCBL/MP is high, RSV0/1 are pulled high. The
following signals are floating: IACK, DX0, FSX0, CLKX0, TCLK1, STRB,
D8-D31, H3, HOLDA, A19-A23, PAGE0, PAGE2.

READY & INT0-3 tied to PLD (HIGH).

We have tried different termination settings inside the FLEXDS pod; but
didn't see any positive change.

The EZDSP has a PLD that the JTAG signals go thru and we don't have the
programming info to determine what is being done in it.

Any suggestions for changes or things to try would be greatly appreciated.

We have looked at the JTAG signals and they appear clean; TDO tri-states
straight out of the VC33 (whereas the EZDSP buffers it, so it stays high).
I guess the bus keeper logic isn't on the JTAG signals.

Regards,

Bill Priest
Applied Concepts Inc.
+-----------+
|Keith Larson |
|Member Group Technical Staff |
|Texas Instruments Incorporated |
| |
| 281-274-3288 |
| |
| www.micro.ti.com/~klarson |
|-----------+
| TMS320C3x/C4x/VC33 Applications |
| |
| TMS320VC33 |
| The lowest cost and lowest power 500 w/Mflop |
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+-----------+


Reply by priestwilliaml September 26, 20022002-09-26
All,
We have two target boards (one in-house developed and one COTS
Spectrum Digital EZDSP) for the TMS320VC33. The emulator and code
composer work fine w/ the EZDSP; however we run into problems on
our target board.

System
TMS320VC33 -120 running in CLKMD0/1 => 11 (ie x5) PLL w/ 11.4 MHz crystal

4Mb Flash (x8 configuration) page1

CPLD attached to lower 8 bits of data bus and lower 4 addr bus page3

TI Bus supervisor chips one for 3.3 & one for 1.8 (cascaded per data
sheet)

JTAG connected directly to processor w/ 4.74K Ohm pull ups on TMS,
TDI, EMU0 & EMU1, 10K Ohm pull down on TRST, TCK tied to TCK_RET,
connector is < 0.5 inches from VC33 jtag pin side.

Board has w/ 2 split power planes (3.3/1.8 under VC33), 1 GND, 2
signal, no active signals under signals from JTAG & VC33.

Symptoms
Code composer comes up and can run simple program loaded at 0x800000
that toggles XF0, which isn't attached to anything. XF0 toggles on
the scope so we know that the program is running. If you hit stop
then the emulator stops and as long as you don't have a disassembly
window open it can be restarted or CPU status registers or memory
window can be paged through. If a disassembly window is open then
the JTAG appears to time out (no messages are displayed other than
the disassembly window contains 0x00000BAD for all addresses starting
at 0x0800000). The emulator responds appropriately to DSP Reset and
"acts" normally afterward (except for displaying disassembly window
after running).

The same sequence using the EZDSP works flawlessly.

We have verified that RESET is high, the clock is stable, SHZ is high,
Edgemode is grounded, MCBL/MP is high, RSV0/1 are pulled high. The
following signals are floating: IACK, DX0, FSX0, CLKX0, TCLK1, STRB,
D8-D31, H3, HOLDA, A19-A23, PAGE0, PAGE2.

READY & INT0-3 tied to PLD (HIGH).

We have tried different termination settings inside the FLEXDS pod;
but didn't see any positive change.

The EZDSP has a PLD that the JTAG signals go thru and we don't have
the programming info to determine what is being done in it.

Any suggestions for changes or things to try would be greatly
appreciated.

We have looked at the JTAG signals and they appear clean; TDO
tri-states straight out of the VC33 (whereas the EZDSP buffers it,
so it stays high). I guess the bus keeper logic isn't on the
JTAG signals.

Regards,

Bill Priest
Applied Concepts Inc.