On Mar 28, 8:41�am, Robert Adams <robert.ad...@analog.com> wrote:
> On Mar 28, 4:31�am, rickman <gnu...@gmail.com> wrote:
>
>
>
> > On Mar 27, 10:34 pm, Eric Jacobsen <eric.jacob...@ieee.org> wrote:
>
> > > On Fri, 27 Mar 2009 16:03:09 -0700 (PDT), rickman <gnu...@gmail.com>
> > > wrote:
>
> > > >On Mar 27, 1:25 pm, Eric Jacobsen <eric.jacob...@ieee.org> wrote:
>
> > > >> Also sometimes called a "delay-locked loop".
>
> > > >I am pretty sure that this is not a delay locked loop. �A DLL uses a
> > > >delay in the feedback path to generate an output that has a different
> > > >phase than the original. �This is often used to compensate for a delay
> > > >elsewhere in the clock path.
>
> > > >In one incarnation of the design of this circuit the error integrator
> > > >was enabled by the input clock enable. �If there was a phase shift in
> > > >the input and output clock enables, it would produce a single count of
> > > >difference during part of the cycle, but would be zero again by the
> > > >next input clock enable. �However, with the phase accumulator (DCO)
> > > >operating on each cycle of the main clock, this single count would be
> > > >added in producing what amounted to a fractional phase step compared
> > > >to the value in the error integrator. �The result is that the smallest
> > > >adjustments in output frequency would be made by the phasing of the
> > > >input and output signals. �However, the phase would never be corrected
> > > >in the error integrator.
>
> > > >This is a bit hard to describe in words. �I hope it is clear.
>
> > > >Rick
>
> > > That's also a DLL, and perhaps the more commonly-used meaning of the
> > > term in my experience.
>
> > Yeah, I guess people use whatever term they want often and that makes
> > it hard to communicate about these things. �I am pretty sure that the
> > "correct" definition of a Delay Locked Loop is as I described above.
> > But if there is no "official" group to decide these things, there
> > really is no correct definition.
>
> > > This FIFO thing is also pretty common but doesn't seem to have a
> > > universal name. � As John mentioned, they've been referred to as RLLs,
> > > "Elastic buffer", and I've heard DLL when the purpose was to match the
> > > delay to some other output to which the stream needs to be
> > > synchronized. �In the satellite world there's also "plesiochronous
> > > buffer" (one of my fave names for this).
>
> > In my case the use is two fold. �I am receiving a bit stream and I
> > need to interleave other data with it at a odd ratio (31:1, 15:1,
> > etc). �The interleave ratio also determines a delay in the other bit
> > stream which must be compensated for in the first bit stream with a
> > fixed quantity delay. �Then as the first bit stream speeds or slows,
> > the second bit stream clock rate is adjusted to match. �The second bit
> > rate is just a simple ratio to the first, so that would not require a
> > PLL. �But the output stream is now 32/31 times the bit rate of the
> > first input. �This is what the PLL is for.
>
> > At the other end a similar circuit de-interleaves the two bit streams
> > and a PLL generates the output clock. �A similar FIFO adds a delay at
> > this end and the FIFO data count is again used as the phase
> > detector.
>
> > > I guess since the jobs that it does can different a universal name is
> > > impractical.
>
> > I would like to think that the name would be based on how the circuit
> > works, not so much on what it is used for. �A FIFO is always called a
> > FIFO (or a queue) regardless of how it is being used. �Oh, well. �The
> > main thing is to get it to work.
>
> > Rick- Hide quoted text -
>
> > - Show quoted text -
>
> One drawback of the "buffer-half-full" control loop is that the jitter
> present on the DCO depends on how "bursty" the input data is.
>
> An alternative approach which is used in sending data over bursty
> channels link Ethernet is the concept of a "time stamp". Assume that
> evey so often (8 samples or so) you interleave a time stamp with the
> data. The time stamp is simply a counter running from the local clock
> that has enough bits that it never wraps around.
>
> So you take this stream and put it through some bursty channel which
> is potentially interleaved with other streams that compete for
> bandwidth. Assume you have some mechanism on the remote node for
> deriving a copy of the "global time", so there is a counter which is
> synced pretty closely with the source counter.
>
> So you put your data into a buffer as before, but now whenever you
> clock out a data sample that has an associated time stamp, you compare
> the time stamp with the local time, and you adjust your DCO based on
> this difference.
>
> So how is this different than the "buffer-half-full" scheme? The
> difference is that the jitter of the dco, in the case where your data
> is very bursty, is independant of the burstiness. You still need a
> buffer large enough to handle the burstiness, but you end up only
> making very small changes to the dco in order to make it track.
>
> There are many networking standards that take this approach, for
> example you can google "Ethernet AVB".
>
> Bob Adams
Isn't this what the low pass filter helps with? Even if the packets
arrive at very random times, the LPF will smooth the control "voltage"
to the DCO. In my case I don't expect a lot of jitter from the input
signal. On the other end, I am not handling the packet interface. My
customer's equipment is doing that. I am supplied with data and
clock. I just have to separate the two data streams and reclock the
output with the fixed delay line.
In another approach, I have to provide a fixed time delay independent
of the data rate. In that case the error integrator is removed and
the buffer length directly controls the DCO rate. I expect that will
not have stability issues.
Rick
Reply by Robert Adams●March 28, 20092009-03-28
On Mar 28, 4:31�am, rickman <gnu...@gmail.com> wrote:
> On Mar 27, 10:34 pm, Eric Jacobsen <eric.jacob...@ieee.org> wrote:
>
>
>
>
>
> > On Fri, 27 Mar 2009 16:03:09 -0700 (PDT), rickman <gnu...@gmail.com>
> > wrote:
>
> > >On Mar 27, 1:25 pm, Eric Jacobsen <eric.jacob...@ieee.org> wrote:
>
> > >> Also sometimes called a "delay-locked loop".
>
> > >I am pretty sure that this is not a delay locked loop. �A DLL uses a
> > >delay in the feedback path to generate an output that has a different
> > >phase than the original. �This is often used to compensate for a delay
> > >elsewhere in the clock path.
>
> > >In one incarnation of the design of this circuit the error integrator
> > >was enabled by the input clock enable. �If there was a phase shift in
> > >the input and output clock enables, it would produce a single count of
> > >difference during part of the cycle, but would be zero again by the
> > >next input clock enable. �However, with the phase accumulator (DCO)
> > >operating on each cycle of the main clock, this single count would be
> > >added in producing what amounted to a fractional phase step compared
> > >to the value in the error integrator. �The result is that the smallest
> > >adjustments in output frequency would be made by the phasing of the
> > >input and output signals. �However, the phase would never be corrected
> > >in the error integrator.
>
> > >This is a bit hard to describe in words. �I hope it is clear.
>
> > >Rick
>
> > That's also a DLL, and perhaps the more commonly-used meaning of the
> > term in my experience.
>
> Yeah, I guess people use whatever term they want often and that makes
> it hard to communicate about these things. �I am pretty sure that the
> "correct" definition of a Delay Locked Loop is as I described above.
> But if there is no "official" group to decide these things, there
> really is no correct definition.
>
> > This FIFO thing is also pretty common but doesn't seem to have a
> > universal name. � As John mentioned, they've been referred to as RLLs,
> > "Elastic buffer", and I've heard DLL when the purpose was to match the
> > delay to some other output to which the stream needs to be
> > synchronized. �In the satellite world there's also "plesiochronous
> > buffer" (one of my fave names for this).
>
> In my case the use is two fold. �I am receiving a bit stream and I
> need to interleave other data with it at a odd ratio (31:1, 15:1,
> etc). �The interleave ratio also determines a delay in the other bit
> stream which must be compensated for in the first bit stream with a
> fixed quantity delay. �Then as the first bit stream speeds or slows,
> the second bit stream clock rate is adjusted to match. �The second bit
> rate is just a simple ratio to the first, so that would not require a
> PLL. �But the output stream is now 32/31 times the bit rate of the
> first input. �This is what the PLL is for.
>
> At the other end a similar circuit de-interleaves the two bit streams
> and a PLL generates the output clock. �A similar FIFO adds a delay at
> this end and the FIFO data count is again used as the phase
> detector.
>
> > I guess since the jobs that it does can different a universal name is
> > impractical.
>
> I would like to think that the name would be based on how the circuit
> works, not so much on what it is used for. �A FIFO is always called a
> FIFO (or a queue) regardless of how it is being used. �Oh, well. �The
> main thing is to get it to work.
>
> Rick- Hide quoted text -
>
> - Show quoted text -
One drawback of the "buffer-half-full" control loop is that the jitter
present on the DCO depends on how "bursty" the input data is.
An alternative approach which is used in sending data over bursty
channels link Ethernet is the concept of a "time stamp". Assume that
evey so often (8 samples or so) you interleave a time stamp with the
data. The time stamp is simply a counter running from the local clock
that has enough bits that it never wraps around.
So you take this stream and put it through some bursty channel which
is potentially interleaved with other streams that compete for
bandwidth. Assume you have some mechanism on the remote node for
deriving a copy of the "global time", so there is a counter which is
synced pretty closely with the source counter.
So you put your data into a buffer as before, but now whenever you
clock out a data sample that has an associated time stamp, you compare
the time stamp with the local time, and you adjust your DCO based on
this difference.
So how is this different than the "buffer-half-full" scheme? The
difference is that the jitter of the dco, in the case where your data
is very bursty, is independant of the burstiness. You still need a
buffer large enough to handle the burstiness, but you end up only
making very small changes to the dco in order to make it track.
There are many networking standards that take this approach, for
example you can google "Ethernet AVB".
Bob Adams
Reply by rickman●March 28, 20092009-03-28
On Mar 27, 10:34 pm, Eric Jacobsen <eric.jacob...@ieee.org> wrote:
> On Fri, 27 Mar 2009 16:03:09 -0700 (PDT), rickman <gnu...@gmail.com>
> wrote:
>
> >On Mar 27, 1:25 pm, Eric Jacobsen <eric.jacob...@ieee.org> wrote:
>
> >> Also sometimes called a "delay-locked loop".
>
> >I am pretty sure that this is not a delay locked loop. A DLL uses a
> >delay in the feedback path to generate an output that has a different
> >phase than the original. This is often used to compensate for a delay
> >elsewhere in the clock path.
>
> >In one incarnation of the design of this circuit the error integrator
> >was enabled by the input clock enable. If there was a phase shift in
> >the input and output clock enables, it would produce a single count of
> >difference during part of the cycle, but would be zero again by the
> >next input clock enable. However, with the phase accumulator (DCO)
> >operating on each cycle of the main clock, this single count would be
> >added in producing what amounted to a fractional phase step compared
> >to the value in the error integrator. The result is that the smallest
> >adjustments in output frequency would be made by the phasing of the
> >input and output signals. However, the phase would never be corrected
> >in the error integrator.
>
> >This is a bit hard to describe in words. I hope it is clear.
>
> >Rick
>
> That's also a DLL, and perhaps the more commonly-used meaning of the
> term in my experience.
Yeah, I guess people use whatever term they want often and that makes
it hard to communicate about these things. I am pretty sure that the
"correct" definition of a Delay Locked Loop is as I described above.
But if there is no "official" group to decide these things, there
really is no correct definition.
> This FIFO thing is also pretty common but doesn't seem to have a
> universal name. As John mentioned, they've been referred to as RLLs,
> "Elastic buffer", and I've heard DLL when the purpose was to match the
> delay to some other output to which the stream needs to be
> synchronized. In the satellite world there's also "plesiochronous
> buffer" (one of my fave names for this).
In my case the use is two fold. I am receiving a bit stream and I
need to interleave other data with it at a odd ratio (31:1, 15:1,
etc). The interleave ratio also determines a delay in the other bit
stream which must be compensated for in the first bit stream with a
fixed quantity delay. Then as the first bit stream speeds or slows,
the second bit stream clock rate is adjusted to match. The second bit
rate is just a simple ratio to the first, so that would not require a
PLL. But the output stream is now 32/31 times the bit rate of the
first input. This is what the PLL is for.
At the other end a similar circuit de-interleaves the two bit streams
and a PLL generates the output clock. A similar FIFO adds a delay at
this end and the FIFO data count is again used as the phase
detector.
> I guess since the jobs that it does can different a universal name is
> impractical.
I would like to think that the name would be based on how the circuit
works, not so much on what it is used for. A FIFO is always called a
FIFO (or a queue) regardless of how it is being used. Oh, well. The
main thing is to get it to work.
Rick
Reply by Allan Herriman●March 28, 20092009-03-28
On Fri, 27 Mar 2009 08:04:43 -0700, rickman wrote:
> I'm sure I'm not the first person to control an oscillator by the amount
> of data in a FIFO, but I haven't found a reference to this design which
> is similar to a PLL.
>
> In place of a typical phase detector, I am using the count of samples in
> the FIFO to control the DCO which drives the output clock. Data is
> clocked into the FIFO using the reference (input) clock. I have an
> integrator between the data count and the DCO phase step input. The
> data count is also offset so that it is zero when at the set point.
>
> I am having trouble understanding how to model this design. Is there a
> unique name for this sort of circuit? At first I was thinking it was a
> frequency locked loop (FLL), but then I realized that the data count
> works the same as a phase detector by integrating the difference in
> frequency of the two signals, it just has a granularity of 1 cycle and
> does not wrap around like typical phase detectors do. So should I be
> using the same model for this as I would use for a conventional PLL
> using a standard phase detector?
>
> I am having trouble getting the circuit to lock in quickly without
> overshoot and hold lock as the frequency shifts. I believe I need to
> add a proportional element to the feedback loop. I am also considering
> using different coefficients when the loop is locked and when not
> locked.
>
> Am I making this hard and it just needs to be treated like any other
> PLL?
Hi Rick,
I've done this sort of thing in a few real-world designs. The FIFO is a
phase / frequency detector when used this way, and the regular PLL theory
applies.
I break the PFD implementations into a number of types:
1. The "half full" output of the FIFO is used as the phase error
signal. This gives bang-bang control, which can result in a chaotic
system. These are hard to analyse, but can still be made to give good
results. Things like jitter gain will vary with input jitter amplitude.
(This doesn't apply to your design, and I won't consider it further.)
2a. The depth output of the FIFO is used to give a (more or less) linear
phase error signal. The FIFO will have stops at either end (writes
disabled if full and reads disabled if empty) which means that the FIFO
also acts as a frequency detector (e.g. if there is a constant difference
in the input and output frequencies, the phase error signal will have an
average value that is non-zero). Note that the frequency detector
doesn't work in a linear way: it is either +max, -max, or off (and the
FIFO is operating as a phase detector with a linear output).
2b. Like 2a, but without the stops. This disables the frequency
detector action of the FIFO. You will need some other sort of frequency
detector to enable the loop to lock. This can be handy if you want to
avoid windup.
> So should I be
> using the same model for this as I would use for a conventional PLL
> using a standard phase detector?
Yes. For both 2a and 2b, you can calculate the equivalent phase detector
gain in terms of output units per radian of phase error. Analog phase
detectors have a gain usually measured in volt / radian or amp / radian
(for charge pump types). If you wish, you can convert units to volts to
enable you to plug your design into old-fashioned PLL design equations.
> I am having trouble getting the circuit to lock in quickly without
> overshoot and hold lock as the frequency shifts. I believe I need to
> add a proportional element to the feedback loop.
Yes, in a Type II system you *need* a zero (from the proportional
element) to position the closed loop poles in a good location. (BTW, the
Type II system has two (open loop) integrators: one is the integrator in
your loop filter, the other is the DCO.)
> I am also considering
> using different coefficients when the loop is locked and when not
> locked.
When used as a frequency detector, the FIFO depth output will be stuck at
+max or -max as long as the frequency difference is present. You can
vary the relative frequency detector / phase detector gain by varying the
depth of your FIFO. A deeper FIFO means that +max and -max will be
larger, and they will slew your integrator faster (meaning lock time will
be lower).
It is also possible to go the other way and reduce the effective
frequency detector "gain" by clipping the PFD output to smaller limits.
When locked, the PFD output only needs to be linear over a limited range,
given by the amount of jitter you need to absorb outside the loop
bandwidth. This is typically small (perhaps a few cycles?). Clipping
the PFD output so that it can't go outside this range can help to reduce
windup effects and improve the overshoot during initial frequency
acquisition, at the cost of increased lock time.
Regards,
Allan
Reply by Tim Wescott●March 27, 20092009-03-27
On Fri, 27 Mar 2009 16:10:07 -0700, rickman wrote:
> > > I'm sure I'm not the first person to control an oscillator by the
> > > amount of data in a FIFO, but I haven't found a reference to this
> > > design which is similar to a PLL.
>
> > > In place of a typical phase detector, I am using the count of
samples
> > > in the FIFO to control the DCO which drives the output clock. Data
is
> > > clocked into the FIFO using the reference (input) clock. I have an
> > > integrator between the data count and the DCO phase step input. The
> > > data count is also offset so that it is zero when at the set point.
>
> > > I am having trouble understanding how to model this design. Is
there
> > > a unique name for this sort of circuit? At first I was thinking it
> > > was a frequency locked loop (FLL), but then I realized that the data
> > > count works the same as a phase detector by integrating the
difference
> > > in frequency of the two signals, it just has a granularity of 1
cycle
> > > and does not wrap around like typical phase detectors do. So
should I
> > > be using the same model for this as I would use for a conventional
PLL
> > > using a standard phase detector?
>
> > > I am having trouble getting the circuit to lock in quickly without
> > > overshoot and hold lock as the frequency shifts. I believe I need
to
> > > add a proportional element to the feedback loop. I am also
> > > considering using different coefficients when the loop is locked and
> > > when not locked.
>
> > > Am I making this hard and it just needs to be treated like any other
> > > PLL?
>
> > > Rick
>
> > Sure sounds like it's just a phase detector. That said, unless every
> > clock of the input clock is putting a sample into the FIFO you start
> > giving away gain pretty rapidly. In a digital feedback loop,
> > gain=bits=ability to treat things as mathematically perfect rather
than
> > mucking around in non-linear quantization effects.
>
> I'm not sure I understand this. Every clock of the input *does* put a
> value into the FIFO. Every clock of the output removes a sample from
> the FIFO.
>
> One thing that is confusing me is that I want to update the error
> integrator only on the input clock enable, but the output clock phase
> accumulator operates on every cycle of the main clock. So a single
> count in the error value produces multiple counts of offset in the
> phase of the output. This seems to make the output rate never
> stabilize completely. I suspect that I need to provide proper low
> pass filtering which I don't currently use.
>
> Rick
On Fri, 27 Mar 2009 08:04:43 -0700, rickman wrote:
> I'm sure I'm not the first person to control an oscillator by the amount
> of data in a FIFO, but I haven't found a reference to this design which
> is similar to a PLL.
>
> In place of a typical phase detector, I am using the count of samples in
> the FIFO to control the DCO which drives the output clock. Data is
> clocked into the FIFO using the reference (input) clock. I have an
> integrator between the data count and the DCO phase step input. The
> data count is also offset so that it is zero when at the set point.
>
> I am having trouble understanding how to model this design. Is there a
> unique name for this sort of circuit?
I don't believe so, but I'm not good with names.
> At first I was thinking it was a
> frequency locked loop (FLL), but then I realized that the data count
> works the same as a phase detector by integrating the difference in
> frequency of the two signals, it just has a granularity of 1 cycle and
> does not wrap around like typical phase detectors do. So should I be
> using the same model for this as I would use for a conventional PLL
> using a standard phase detector?
Yes and no. It doesn't wrap, but it does quantize. So you still need to
model the offset accumulation process as an integration, but you don't
need to model the phase accumulator rollover, and you do need to model
quantization one way or another.
> I am having trouble getting the circuit to lock in quickly without
> overshoot and hold lock as the frequency shifts. I believe I need to
> add a proportional element to the feedback loop.
You sure do! How well does a double integrator loop with no damping
settle, after all?
> I am also considering
> using different coefficients when the loop is locked and when not
> locked.
That may be wise.
> Am I making this hard and it just needs to be treated like any other
> PLL?
>
> Rick
I think you're overanalyzing some simple things, and overlooking some
complexities. You should be able to _leverage_ your knowledge of PLL
theory, but you have to modify it wisely to make it work in this case.
--
http://www.wescottdesign.com
Reply by Eric Jacobsen●March 27, 20092009-03-27
On Fri, 27 Mar 2009 16:03:09 -0700 (PDT), rickman <gnuarm@gmail.com>
wrote:
>On Mar 27, 1:25�pm, Eric Jacobsen <eric.jacob...@ieee.org> wrote:
>> On Fri, 27 Mar 2009 08:19:43 -0700 (PDT), John <sampson...@gmail.com>
>> wrote:
>>
>>
>>
>> >On Mar 27, 11:04�am, rickman <gnu...@gmail.com> wrote:
>> >> I'm sure I'm not the first person to control an oscillator by the
>> >> amount of data in a FIFO, but I haven't found a reference to this
>> >> design which is similar to a PLL.
>>
>> >> In place of a typical phase detector, I am using the count of samples
>> >> in the FIFO to control the DCO which drives the output clock. �Data is
>> >> clocked into the FIFO using the reference (input) clock. �I have an
>> >> integrator between the data count and the DCO phase step input. �The
>> >> data count is also offset so that it is zero when at the set point.
>>
>> >> I am having trouble understanding how to model this design. �Is there
>> >> a unique name for this sort of circuit? �At first I was thinking it
>> >> was a frequency locked loop (FLL), but then I realized that the data
>> >> count works the same as a phase detector by integrating the difference
>> >> in frequency of the two signals, it just has a granularity of 1 cycle
>> >> and does not wrap around like typical phase detectors do. �So should I
>> >> be using the same model for this as I would use for a conventional PLL
>> >> using a standard phase detector?
>>
>> >> I am having trouble getting the circuit to lock in quickly without
>> >> overshoot and hold lock as the frequency shifts. �I believe I need to
>> >> add a proportional element to the feedback loop. �I am also
>> >> considering using different coefficients when the loop is locked and
>> >> when not locked.
>>
>> >> Am I making this hard and it just needs to be treated like any other
>> >> PLL?
>>
>> >> Rick
>>
>> >I call it a "rate-locked loop", but I'm not sure there is an official
>> >name. Other keywords include "elastic store" or "elastic buffer".
>>
>> >You can write loop equations and get response curves. If the buffer
>> >length is B, the error is (x - B/2)/(B/2) where x is how much is in
>> >the buffer. The feedback is through a standard lead-lag filter, the
>> >output of which controls the buffer's empty rate.
>>
>> >John
>>
>> Also sometimes called a "delay-locked loop".
>
>I am pretty sure that this is not a delay locked loop. A DLL uses a
>delay in the feedback path to generate an output that has a different
>phase than the original. This is often used to compensate for a delay
>elsewhere in the clock path.
>
>In one incarnation of the design of this circuit the error integrator
>was enabled by the input clock enable. If there was a phase shift in
>the input and output clock enables, it would produce a single count of
>difference during part of the cycle, but would be zero again by the
>next input clock enable. However, with the phase accumulator (DCO)
>operating on each cycle of the main clock, this single count would be
>added in producing what amounted to a fractional phase step compared
>to the value in the error integrator. The result is that the smallest
>adjustments in output frequency would be made by the phasing of the
>input and output signals. However, the phase would never be corrected
>in the error integrator.
>
>This is a bit hard to describe in words. I hope it is clear.
>
>Rick
That's also a DLL, and perhaps the more commonly-used meaning of the
term in my experience.
This FIFO thing is also pretty common but doesn't seem to have a
universal name. As John mentioned, they've been referred to as RLLs,
"Elastic buffer", and I've heard DLL when the purpose was to match the
delay to some other output to which the stream needs to be
synchronized. In the satellite world there's also "plesiochronous
buffer" (one of my fave names for this).
I guess since the jobs that it does can different a universal name is
impractical.
Eric Jacobsen
Minister of Algorithms
Abineau Communications
http://www.ericjacobsen.org
Blog: http://www.dsprelated.com/blogs-1/hf/Eric_Jacobsen.php
Reply by John●March 27, 20092009-03-27
On Mar 27, 7:10�pm, rickman <gnu...@gmail.com> wrote:
> On Mar 27, 12:32�pm, Rob Gaddi <rga...@technologyhighland.com> wrote:
>
>
>
> > On Fri, 27 Mar 2009 08:04:43 -0700 (PDT)
>
> > rickman <gnu...@gmail.com> wrote:
> > > I'm sure I'm not the first person to control an oscillator by the
> > > amount of data in a FIFO, but I haven't found a reference to this
> > > design which is similar to a PLL.
>
> > > In place of a typical phase detector, I am using the count of samples
> > > in the FIFO to control the DCO which drives the output clock. �Data is
> > > clocked into the FIFO using the reference (input) clock. �I have an
> > > integrator between the data count and the DCO phase step input. �The
> > > data count is also offset so that it is zero when at the set point.
>
> > > I am having trouble understanding how to model this design. �Is there
> > > a unique name for this sort of circuit? �At first I was thinking it
> > > was a frequency locked loop (FLL), but then I realized that the data
> > > count works the same as a phase detector by integrating the difference
> > > in frequency of the two signals, it just has a granularity of 1 cycle
> > > and does not wrap around like typical phase detectors do. �So should I
> > > be using the same model for this as I would use for a conventional PLL
> > > using a standard phase detector?
>
> > > I am having trouble getting the circuit to lock in quickly without
> > > overshoot and hold lock as the frequency shifts. �I believe I need to
> > > add a proportional element to the feedback loop. �I am also
> > > considering using different coefficients when the loop is locked and
> > > when not locked.
>
> > > Am I making this hard and it just needs to be treated like any other
> > > PLL?
>
> > > Rick
>
> > Sure sounds like it's just a phase detector. �That said, unless every
> > clock of the input clock is putting a sample into the FIFO you start
> > giving away gain pretty rapidly. �In a digital feedback loop,
> > gain=bits=ability to treat things as mathematically perfect rather than
> > mucking around in non-linear quantization effects.
>
> I'm not sure I understand this. �Every clock of the input *does* put a
> value into the FIFO. �Every clock of the output removes a sample from
> the FIFO.
>
> One thing that is confusing me is that I want to update the error
> integrator only on the input clock enable, but the output clock phase
> accumulator operates on every cycle of the main clock. �So a single
> count in the error value produces multiple counts of offset in the
> phase of the output. �This seems to make the output rate never
> stabilize completely. �I suspect that I need to provide proper low
> pass filtering which I don't currently use.
>
> Rick
Here's a simulation in Matlab that shows output rate adaptation to
keep buffer half full.
John
nco_fill=1;
nco_empty=1;
% write rate is 1/3
phinc_fill=1/3;
% read rate offset from write rate by 'ppm'
ppm=100;
phinc_empty=phinc_fill*(1+ppm/1e6);
pherr=0;
Ki=1/1000;
Kp=1/10;
acc=0;
N=1e5;
backlog=0;
bv = zeros(N,1);sv=bv;nf=bv;ne=bv;ev=bv;
% buffer size is B
B=1000;
state=0;
for k = 1:N
if(nco_fill-phinc_fill<=0)
% write a sample into buffer when fill nco wraps
backlog = backlog + 1;
nco_fill = 1-abs(nco_fill-phinc_fill);
else
nco_fill=nco_fill-phinc_fill;
end
if(state == 0)
% state 0: waiting for half full condition
if(backlog > B/2)
state = 1;
end
elseif(state == 1)
% state 1: emptying
nco_empty=nco_empty-phinc_empty-pherr;
if(nco_empty<=0)
% read a sample from buffer when empty nco wraps
backlog = backlog-1;
nco_empty=1-abs(nco_empty-phinc_empty-pherr);
end
% compute error and apply to PI filter
e = (backlog-B/2)/(B/2);
acc = Kp*e + acc;
lag = Ki*acc;
lead = Kp*e;
pherr = lag + lead;
end
bv(k) = backlog;
end
plot(bv);grid;shg;title('Backlog');
Reply by rickman●March 27, 20092009-03-27
On Mar 27, 12:32�pm, Rob Gaddi <rga...@technologyhighland.com> wrote:
> On Fri, 27 Mar 2009 08:04:43 -0700 (PDT)
>
>
>
> rickman <gnu...@gmail.com> wrote:
> > I'm sure I'm not the first person to control an oscillator by the
> > amount of data in a FIFO, but I haven't found a reference to this
> > design which is similar to a PLL.
>
> > In place of a typical phase detector, I am using the count of samples
> > in the FIFO to control the DCO which drives the output clock. �Data is
> > clocked into the FIFO using the reference (input) clock. �I have an
> > integrator between the data count and the DCO phase step input. �The
> > data count is also offset so that it is zero when at the set point.
>
> > I am having trouble understanding how to model this design. �Is there
> > a unique name for this sort of circuit? �At first I was thinking it
> > was a frequency locked loop (FLL), but then I realized that the data
> > count works the same as a phase detector by integrating the difference
> > in frequency of the two signals, it just has a granularity of 1 cycle
> > and does not wrap around like typical phase detectors do. �So should I
> > be using the same model for this as I would use for a conventional PLL
> > using a standard phase detector?
>
> > I am having trouble getting the circuit to lock in quickly without
> > overshoot and hold lock as the frequency shifts. �I believe I need to
> > add a proportional element to the feedback loop. �I am also
> > considering using different coefficients when the loop is locked and
> > when not locked.
>
> > Am I making this hard and it just needs to be treated like any other
> > PLL?
>
> > Rick
>
> Sure sounds like it's just a phase detector. �That said, unless every
> clock of the input clock is putting a sample into the FIFO you start
> giving away gain pretty rapidly. �In a digital feedback loop,
> gain=bits=ability to treat things as mathematically perfect rather than
> mucking around in non-linear quantization effects.
I'm not sure I understand this. Every clock of the input *does* put a
value into the FIFO. Every clock of the output removes a sample from
the FIFO.
One thing that is confusing me is that I want to update the error
integrator only on the input clock enable, but the output clock phase
accumulator operates on every cycle of the main clock. So a single
count in the error value produces multiple counts of offset in the
phase of the output. This seems to make the output rate never
stabilize completely. I suspect that I need to provide proper low
pass filtering which I don't currently use.
Rick
Reply by rickman●March 27, 20092009-03-27
On Mar 27, 1:25�pm, Eric Jacobsen <eric.jacob...@ieee.org> wrote:
> On Fri, 27 Mar 2009 08:19:43 -0700 (PDT), John <sampson...@gmail.com>
> wrote:
>
>
>
> >On Mar 27, 11:04�am, rickman <gnu...@gmail.com> wrote:
> >> I'm sure I'm not the first person to control an oscillator by the
> >> amount of data in a FIFO, but I haven't found a reference to this
> >> design which is similar to a PLL.
>
> >> In place of a typical phase detector, I am using the count of samples
> >> in the FIFO to control the DCO which drives the output clock. �Data is
> >> clocked into the FIFO using the reference (input) clock. �I have an
> >> integrator between the data count and the DCO phase step input. �The
> >> data count is also offset so that it is zero when at the set point.
>
> >> I am having trouble understanding how to model this design. �Is there
> >> a unique name for this sort of circuit? �At first I was thinking it
> >> was a frequency locked loop (FLL), but then I realized that the data
> >> count works the same as a phase detector by integrating the difference
> >> in frequency of the two signals, it just has a granularity of 1 cycle
> >> and does not wrap around like typical phase detectors do. �So should I
> >> be using the same model for this as I would use for a conventional PLL
> >> using a standard phase detector?
>
> >> I am having trouble getting the circuit to lock in quickly without
> >> overshoot and hold lock as the frequency shifts. �I believe I need to
> >> add a proportional element to the feedback loop. �I am also
> >> considering using different coefficients when the loop is locked and
> >> when not locked.
>
> >> Am I making this hard and it just needs to be treated like any other
> >> PLL?
>
> >> Rick
>
> >I call it a "rate-locked loop", but I'm not sure there is an official
> >name. Other keywords include "elastic store" or "elastic buffer".
>
> >You can write loop equations and get response curves. If the buffer
> >length is B, the error is (x - B/2)/(B/2) where x is how much is in
> >the buffer. The feedback is through a standard lead-lag filter, the
> >output of which controls the buffer's empty rate.
>
> >John
>
> Also sometimes called a "delay-locked loop".
I am pretty sure that this is not a delay locked loop. A DLL uses a
delay in the feedback path to generate an output that has a different
phase than the original. This is often used to compensate for a delay
elsewhere in the clock path.
In one incarnation of the design of this circuit the error integrator
was enabled by the input clock enable. If there was a phase shift in
the input and output clock enables, it would produce a single count of
difference during part of the cycle, but would be zero again by the
next input clock enable. However, with the phase accumulator (DCO)
operating on each cycle of the main clock, this single count would be
added in producing what amounted to a fractional phase step compared
to the value in the error integrator. The result is that the smallest
adjustments in output frequency would be made by the phasing of the
input and output signals. However, the phase would never be corrected
in the error integrator.
This is a bit hard to describe in words. I hope it is clear.
Rick