On May 30, 10:11�am, rickman <gnu...@gmail.com> wrote:
> On May 30, 5:13 am, Allan Herriman <allanherri...@hotmail.com> wrote:
>
>
>
> > On Fri, 29 May 2009 21:57:44 -0700, rickman wrote:
> > > On May 29, 10:58 pm, robert bristow-johnson <r...@audioimagination.com>
> > > wrote:
> > >> On May 29, 6:53 pm, rickman <gnu...@gmail.com> wrote:
>
> > >> > On May 29, 6:35 pm, makol...@yahoo.com wrote:
>
> > >> > > On May 29, 6:15 pm, rickman <gnu...@gmail.com> wrote:
>
> > >> > > > I posted a message a couple of months ago on a PLL I am working
> > >> > > > on, but I can't continue that thread. �The circuit is using a PLL
> > >> > > > to generate an output clock which is a integer ratio multiple of
> > >> > > > the input clock. �The purpose is to pull data out of a FIFO at
> > >> > > > the same rate it is going in and to keep a fixed amount of data
> > >> > > > in the FIFO while driving the output which is an interleave
> > >> > > > circuit. �So the output clock needs to be N/(N-1) times the input
> > >> > > > clock and the PLL must maintain a zero phase relationship (long
> > >> > > > term) between the input clock and the divided down output clock
> > >> > > > in order to keep amount of data in the FIFO constant.
>
> > >> > > > The circuit I came up with for this uses an up/down counter as
> > >> > > > the phase comparator. �The the leading edge of the input clock
> > >> > > > makes it count up and the leading edge of the feedback clock
> > >> > > > makes it count down. �If both occur during a given system clock
> > >> > > > cycle, the count is held as it is when there are no leading
> > >> > > > edges.
>
> > >> > > > From what I have seen, this is considered a bang-bang phase
> > >> > > > comparator in the analog world. �I guess it works the same in the
> > >> > > > digital world too. �The filter I am using is an integrator added
> > >> > > > to a proportional (each with gain factors) to produce the step
> > >> > > > size fed to the NCO. �The NCO produces a clock enable on overflow
> > >> > > > which feeds the interleave circuit. �The interleave circuit
> > >> > > > returns N-1 out of every N clocks to pull data out of the FIFO
> > >> > > > and feedback to the PLL.
>
> > >> > > > I simulated this with gain settings of A=64 for the proportional
> > >> > > > path and B=1/128 for the integrator output. �I also tried other
> > >> > > > values and they are all stable, but some settle faster and others
> > >> > > > ring more before settling. �I picked the values that seem to give
> > >> > > > me quick settling and track an input frequency change well
> > >> > > > without a lot of oscillation.
>
> > >> > > > All that said, when I do an analysis of the filter using the z-
> > >> > > > transform, I get a pole on the unit circle at 1,0 and a zero very
> > >> > > > close to it at 0.999...,0. �It would appear that the zero is
> > >> > > > stabilizing the pole and frequencies other than very near DC.
> > >> > > > But a DC input is stabilized by the overall loop. �The question
> > >> > > > is, how do I include the rest of the loop in a z-transform
> > >> > > > analysis? �Or is this not the right way to approach it?
>
> > >> > > > Rick
>
> > >> > > First clarification...when you say digital PLL, is this all in DSP,
> > >> > > i.e. is it an NCO �or a VCO with a real control voltage?
>
> > >> > > The full loop is analyzed with the KVco the gain of the VCO (or
> > >> > > NCO) and the gain of the phase detector. �Since the VCO generates a
> > >> > > frequency and the phase detector detects a phase, the combination
> > >> > > produces a pole at DC or an integrator.
>
> > >> > > Mark
>
> > >> > All digital as in an FPGA. �No VCO and no NCO, it uses a DCO. �I was
> > >> > mistaken when I used the term NCO.
>
> > >> what's the difference between a Numerically-Controlled Oscillator and a
> > >> Digitally-Controlled Oscillator?
>
> > > I didn't think there was any, but it was explained to me that an NCO has
> > > the lookup table to generate a sine/cosine output while a DCO just
> > > provides either the upper bit to generate a square wave, or the carry
> > > out to generate a one pulse per roll over. �I used to use them
> > > interchangeably, but I found this difference documented somewhere on the
> > > web, so it must be true.
>
> > >> > There is also an integrator in the filter. �The filter integrator is
> > >> > necessary to drive the error output of the phase comparator to zero.
>
> > >> but there is also an inherent integrator in the DCO.
>
> > > Yes, I wasn't trying to say this was different, just to get the
> > > terminology correct. �He was asking if it was a hardware VCO or
> > > something else.
>
> > >> > When you say the DCO and phase comparator produce a pole at DC, where
> > >> > exactly is this DC determined? �Are you referring to a DC input as in
> > >> > 0 Hz? �I believe if you have a 0 Hz input and your filter does not
> > >> > include an integrator, the output will be 0 Hz. �Am I missing
> > >> > something?
>
> > >> i am not sure if you're missing this or not, but in case you are,
> > >> please lemme spell it out:
>
> > >> 1. the output frequency of the DCO is presumed to be proportional to
> > >> the input control paramenter.
>
> > >> 2. frequency is the derivative of phase w.r.t. time. �that means if you
> > >> are going to relate *unwrapped* phase to frequency it's like the
> > >> frequency parameter goes into an integrator and out comes phase.
>
> > >> 3. the phase comparator compares the phase of the output of the DCO to
> > >> the input waveform (which we assume is periodic) and gives you a result
> > >> which is a number (or a pseudo-"voltage") which is proportional to that
> > >> phase difference.
>
> > >> 4. that phase difference is fed back through whatever gain and whatever
> > >> other LTI system (or it might not all be linear, you might want to put
> > >> some hard limiting in there or something else to help you hunt and lock
> > >> when the frequencies are widely different). �because in a discrete-time
> > >> system we cannot have a closed loop with zero delay (we only know the
> > >> previous output values to be used in the computation of the current
> > >> input, we cannot know the current output for the current input), then
> > >> there is necessarily a delay element in that feedback LTI system *must*
> > >> have an overall 1/z factor in it.
>
> > >> 5. so, even with the simplest proportional controller (no I or D in the
> > >> PID), you will necessarily have an integrator (1/(1-1/z)) and another
> > >> delay (1/z) in the loop. �that cannot be avoided. �now, if you choose
> > >> to add more stuff than a P in your PID controller, you may, but your
> > >> loop gain must have at least a 1/z * 1/(1-1/z) in it.
>
> > >> dunno if any of this is helpful.
>
> > >> r b-j
>
> > > Thanks for the info. �I am aware of everything you wrote. �I just am
> > > having trouble doing the math for it. �My "filter" only needs an
> > > integrator which will allow the error signal out of the phase detector
> > > to become zero for any given frequency input. �But this is not a stable
> > > configuration. �I added a proportional feedback which helps to stabilize
> > > the loop. �I can analyze the filter, but I'm not clear on how to analyze
> > > the entire loop.
>
> > Rick, can you clarify something please? �Are you having a problem with
> > the algebra, or are you having a problem with modelling the design?
>
> > By "the algebra" I mean turning the transfer functions of the various
> > parts (loop filter, nco, etc.) into a transfer function of the entire
> > system.
>
> > By "modelling the design", I mean turning your implementation of the
> > various parts (e.g. adders, counters, accumulators, etc.) into transfer
> > functions. �If you haven't done this before, it may not be immediately
> > obvious how to work out something like Kv for your NCO or the phase
> > detector gain.
>
> > Thanks,
> > Allan
>
> The modeling. �I don't have trouble with algebra. �I did retain that
> bit from school.
>
> I'm not worried about Kv or Kp. �I am not clear on whether I should
> treat which element as an integrator (the DCO clearly seems to be, but
> I'm not sure about the phase comparator) and how to construct the
> overall equation.
>
> Rick
In a mathematical PLL model, one typically derives H(z)=Y(z)/X(z)
where Y(z) is the phase of the input signal and X(z) is the phase of
the NCO. With this approach, the phase detector is just a scale
factor, P(z)=Kv. A PI loop filter can be modeled as F(z)=Kp*(1+Ki/
(z-1)). The NCO can be modeled as N(z)=z/(z-1).
The open loop TF is G(z)=Kv*F(z)*N(z)/z where the extra 1/z accounts
for computational delay as mentioned in another post. The closed loop
TF is H(z)=G(z)/(1+G(z)).
John