Reply by Darrell June 22, 20092009-06-22
On Jun 19, 7:12&#4294967295;pm, Al Clark <acl...@danvillesignal.com> wrote:
> > Clay Turner's excellent article discusses this in the current IEEE Signal > Processing Magazine which I received on Wednesday.
Funny! I haven't received my copy yet but I'll be sure to look for it. I was trying to remember where I first learned the trick, and best I could recall it was either this newsgroup or Frerking's book. I guess it must have been Clay :-). Darrell
Reply by Al Clark June 19, 20092009-06-19
Darrell <darrelljs@gmail.com> wrote in news:276159ca-f1ec-42f4-b155-
4a22f646294e@n4g2000vba.googlegroups.com:

>> > On 12 June, 01:35, robert bristow-johnson <r...@audioimagination.com> >> > wrote: >> >> with halfband symmetry, those 100 taps are interlaced with zero-valued >> taps, so the "reach" of the impulse response is about 200 taps. &#4294967295;when >> you give up on symmetry, you lose those zero taps and then you have to >> pay for computing them. &#4294967295;also, while this makes little difference with >> a DSP, in an FPGA you can take advantage of symmetry in the IR and >> have half (again) as many multiplications even though you still have >> the same number of memory accesses and additions. > > Another trick with halfband filters that may or may not help...design > a > sub-spec half-band filter and modulate it by one sinusoid with a phase > of -pi/4 > and another with a phase of pi/4. This will give you two "Hilbert" > transformers > that are -45 degrees and + 45 degrees (i.e. still 90 degrees out of > phase). > The advantage of doing it this way is that the amplitude response of > the two > filters are identical. For some applications (e.g. magnitude > estimation) the > problem isn't the ripple, it is the mismatched amplitude response > between the > I and Q path... > > Darrell > > P.S. There is a bit more to it since you need to ensure the center tap > is > sqrt(2)/2, and if this is something you are interested in I'll post > the details. >
Clay Turner's excellent article discusses this in the current IEEE Signal Processing Magazine which I received on Wednesday. Al Clark Danville Signal
Reply by Darrell June 19, 20092009-06-19
> > On 12 June, 01:35, robert bristow-johnson <r...@audioimagination.com> > > wrote: > > with halfband symmetry, those 100 taps are interlaced with zero-valued > taps, so the "reach" of the impulse response is about 200 taps. &#4294967295;when > you give up on symmetry, you lose those zero taps and then you have to > pay for computing them. &#4294967295;also, while this makes little difference with > a DSP, in an FPGA you can take advantage of symmetry in the IR and > have half (again) as many multiplications even though you still have > the same number of memory accesses and additions.
Another trick with halfband filters that may or may not help...design a sub-spec half-band filter and modulate it by one sinusoid with a phase of -pi/4 and another with a phase of pi/4. This will give you two "Hilbert" transformers that are -45 degrees and + 45 degrees (i.e. still 90 degrees out of phase). The advantage of doing it this way is that the amplitude response of the two filters are identical. For some applications (e.g. magnitude estimation) the problem isn't the ripple, it is the mismatched amplitude response between the I and Q path... Darrell P.S. There is a bit more to it since you need to ensure the center tap is sqrt(2)/2, and if this is something you are interested in I'll post the details.
Reply by Robert Orban June 18, 20092009-06-18
In article <4c3b3c23-b833-461c-877e-
4de454c9933d@o18g2000yqi.googlegroups.com>, stenasc@yahoo.com says...
> > >Hi, > >I'm implementing a HT with sampling freq 2 Mhz to convert a real >signal to complex.. The required passband goes down all the way to 50 >hz. I have a couple of questions which hopefully the experts can give >me some advice. First of all. to get the required frequency response >and to keep the passband ripple as low as possible, I need a large >number of taps and this uses a lot of resources on an FPGA. Is there a >quick and dirty method to implement a HT which will reduce the number >of resources required? Would running the input signal through a simple >delay line to get the 90 degree phase shift work? I've thought about >it and I don't think it would because I don't think it would filter >out the negative frequencies but I would like confirmation of this or >not. > > >Tapping output from the centre tap...Can this output be just the input >delayed or does it have to be the result of the input convolved with >half the filter coefficients.
Fast convolution comes to mind. The big challenge with a filter like this is computing the tap weights (if you want minimax result) because the MPR algorithm tends to break down when more than a few thousand taps are computed. I have done quick and dirty wideband HTs by doing FFTs on large blocks (~64000 samples), swapping the real and imaginary parts, negating the new imaginary part, and doing an IFFT. I threw away about 3000 samples at each end and crossfaded between blocks. When used for SSB modulation, results were surprisingly good (unwanted sideband suppression was somewhere better than -80 dB IIRC) even though the technique does not not meet the strict criteria for overlap and add.
Reply by Clay June 15, 20092009-06-15
On Jun 13, 6:08&#4294967295;pm, Bob <sten...@yahoo.com> wrote:
> On 12 June, 16:00, Clay <c...@claysturner.com> wrote: > > > > > > > On Jun 11, 10:39&#4294967295;am, Bob <sten...@yahoo.com> wrote: > > > > Hi, > > > > I'm implementing a HT with sampling freq 2 Mhz to convert a real > > > signal to complex.. The required passband goes down all the way to 50 > > > hz. I have a couple of questions which hopefully the experts can give > > > me some advice. First of all. to get the required frequency response > > > and to keep the passband ripple as low as possible, I need a large > > > number of taps and this uses a lot of resources on an FPGA. Is there a > > > quick and dirty method to implement a HT which will reduce the number > > > of resources required? Would running the input signal through a simple > > > delay line to get the 90 degree phase shift work? I've thought about > > > it and I don't think it would because I don't think it would filter > > > out the negative frequencies but I would like confirmation of this or > > > not. > > > > Tapping output from the centre tap...Can this output be just the input > > > delayed or does it have to be the result of the input convolved with > > > half the filter coefficients. > > > > Many Thanks > > > Bob Carter > > > Hello Bob, > > > You have one set of crazy specs! I assume you are trying to make an > > analytic signal, so how about subdividing your original signal into > > bands using quadrature mirror filters with appropriate decimation > > after each bandsplit, and then forming each of these band outputs into > > analytic signals. Then when appropriately combined (after applying > > proper delays and interpolation) you can make your wideband analytic > > signal. But this may take several FPGAs. I don't think there is an > > easy answer to your problem without somehow relaxing your spec. Does > > your signal processing really require such a bandwidth all at the same > > time? Or does your process use a smaller bandwidth but just needs to > > be frequency agile? If you can reduce the bandwidth, then your Hilbert > > problem gets simpler. For efficiently making analytic signals I have > > an article that describes a way to do it that will be availible on > > July 1st in the Signal Processing Magazine. > > > FWIW, > > Clay > > Hi Clay, > > Yeah...trying to make an analytic signal, which is turning out to be a > pain in the analytic area. The quadrature mirror filters idea would > take up a lot of logic on the chip, so I'd rather not go down that > road. It also looks to be a quite complex task and I'll have the usual > time pressures to contend with. I'm currently investigating if I can > relax the bandwidth requirements and R.B.J. has thrown up some > interesting possibilities as well. However, I'm certainly looking > forward to having a read of your article....any chance of a > preview ??? > > Regards > Bob- Hide quoted text - > > - Show quoted text -
I'm afraid it would be poor form to offer up a detailed preview of the article before the publisher gets it out. But it does allow for cutting the number of taps in half and the method has nearly linear phase. Clay
Reply by robert bristow-johnson June 14, 20092009-06-14
On Jun 14, 11:22&#4294967295;am, "wazerf...@gmail.com" <wazerf...@gmail.com>
wrote:
> On Jun 11, 9:39&#4294967295;am, Bob <sten...@yahoo.com> wrote: > > > I'm implementing a HT with sampling freq 2 Mhz to convert a real > > signal to complex.. The required passband goes down all the way to 50 > > hz.
...
> > Can you do quadrature re-sampling?
ooookay. what exactly is it and how does that speak to solution to the problem and not the desired consequence of the solution? r b-j
Reply by waze...@gmail.com June 14, 20092009-06-14
On Jun 11, 9:39&#4294967295;am, Bob <sten...@yahoo.com> wrote:
> Hi, > > I'm implementing a HT with sampling freq 2 Mhz to convert a real > signal to complex.. The required passband goes down all the way to 50 > hz. I have a couple of questions which hopefully the experts can give > me some advice. First of all. to get the required frequency response > and to keep the passband ripple as low as possible, I need a large > number of taps and this uses a lot of resources on an FPGA. Is there a > quick and dirty method to implement a HT which will reduce the number > of resources required? Would running the input signal through a simple > delay line to get the 90 degree phase shift work? I've thought about > it and I don't think it would because I don't think it would filter > out the negative frequencies but I would like confirmation of this or > not. > > Tapping output from the centre tap...Can this output be just the input > delayed or does it have to be the result of the input convolved with > half the filter coefficients. > > Many Thanks > Bob Carter
Can you do quadrature re-sampling?
Reply by Bob June 13, 20092009-06-13
On 12 June, 16:00, Clay <c...@claysturner.com> wrote:
> On Jun 11, 10:39&#4294967295;am, Bob <sten...@yahoo.com> wrote: > > > > > Hi, > > > I'm implementing a HT with sampling freq 2 Mhz to convert a real > > signal to complex.. The required passband goes down all the way to 50 > > hz. I have a couple of questions which hopefully the experts can give > > me some advice. First of all. to get the required frequency response > > and to keep the passband ripple as low as possible, I need a large > > number of taps and this uses a lot of resources on an FPGA. Is there a > > quick and dirty method to implement a HT which will reduce the number > > of resources required? Would running the input signal through a simple > > delay line to get the 90 degree phase shift work? I've thought about > > it and I don't think it would because I don't think it would filter > > out the negative frequencies but I would like confirmation of this or > > not. > > > Tapping output from the centre tap...Can this output be just the input > > delayed or does it have to be the result of the input convolved with > > half the filter coefficients. > > > Many Thanks > > Bob Carter > > Hello Bob, > > You have one set of crazy specs! I assume you are trying to make an > analytic signal, so how about subdividing your original signal into > bands using quadrature mirror filters with appropriate decimation > after each bandsplit, and then forming each of these band outputs into > analytic signals. Then when appropriately combined (after applying > proper delays and interpolation) you can make your wideband analytic > signal. But this may take several FPGAs. I don't think there is an > easy answer to your problem without somehow relaxing your spec. Does > your signal processing really require such a bandwidth all at the same > time? Or does your process use a smaller bandwidth but just needs to > be frequency agile? If you can reduce the bandwidth, then your Hilbert > problem gets simpler. For efficiently making analytic signals I have > an article that describes a way to do it that will be availible on > July 1st in the Signal Processing Magazine. > > FWIW, > Clay
Hi Clay, Yeah...trying to make an analytic signal, which is turning out to be a pain in the analytic area. The quadrature mirror filters idea would take up a lot of logic on the chip, so I'd rather not go down that road. It also looks to be a quite complex task and I'll have the usual time pressures to contend with. I'm currently investigating if I can relax the bandwidth requirements and R.B.J. has thrown up some interesting possibilities as well. However, I'm certainly looking forward to having a read of your article....any chance of a preview ??? Regards Bob
Reply by Bob June 13, 20092009-06-13
On 12 June, 23:42, robert bristow-johnson <r...@audioimagination.com>
wrote:
> On Jun 12, 5:22 am, Bob <sten...@yahoo.com> wrote: > > > > > On 12 June, 01:35, robert bristow-johnson <r...@audioimagination.com> > > wrote: > > > > On Jun 11, 11:30 am, Bob <sten...@yahoo.com> wrote: > > > > > > > I'm implementing a HT with sampling freq 2 Mhz to convert a real signal > > > > > > to complex.. The required passband goes down all the way to 50 hz. > > > > ... > > > > > I'm afraid the bandwidth is wideband... 50 Hz all the way to 700000 Hz. > > > > Whoa, Nellie!!! > > ... > > > > so how long is your FIR? &#4294967295;you *could* use halfband symmetry, but the > > > 50 Hz spec on your bottom will translate to a Nyquist-50Hz spec on the > > > top, which is probably better than you need. > > > > tough spec. > ... > > > There is no way on earth I can meet that spec using a conventional HT. > > no shit. &#4294967295;not without a lot of taps. > > > If I change the passband to 10KHz to 990 KHz and have it symmetrical, > > then I begin to see a decent result using approx 100 taps...which I > > could implement on an FPGA. > > with halfband symmetry, those 100 taps are interlaced with zero-valued > taps, so the "reach" of the impulse response is about 200 taps. &#4294967295;when > you give up on symmetry, you lose those zero taps and then you have to > pay for computing them. &#4294967295;also, while this makes little difference with > a DSP, in an FPGA you can take advantage of symmetry in the IR and > have half (again) as many multiplications even though you still have > the same number of memory accesses and additions. >
A halfband HT...hmm....didn't know such a beast existed...just interlace the coeffs with zeros you say...what happens with the sampling freq...do I double it? I've implemented half bands before to good effect and also taken advantage of IR symmetry to reduce logic count on FPGAs so that's an interesting possibility.
> > However, I need to get the lower edge of > > the passband down closer to 50 Hz. Is there any other way of achieving > > the same effect as a HT &#4294967295;for baseband signals? > > without bumping your signal spectrum up by (10000-50) Hz (and how're > you gonna do that without an HT?) and bumping it back down, i dunno. > maybe the old fashioned way we ham operators used to do it in single- > sideband (SSB) with "mixers" and crystal-lattice filters. &#4294967295;you'll need > some pretty sharp IIR filters. &#4294967295;it might not work so well. &#4294967295;i dunno.
Was thinking of moving up the spectrum and then mixing back down again, but that brings its own problems as you've alluded to above. May have to go down this route yet.
> > it's a damn tough spec.
Let's just say...It a challenging one !!
> > r b-j
Reply by robert bristow-johnson June 12, 20092009-06-12
On Jun 12, 5:22 am, Bob <sten...@yahoo.com> wrote:
> On 12 June, 01:35, robert bristow-johnson <r...@audioimagination.com> > wrote: > > > On Jun 11, 11:30 am, Bob <sten...@yahoo.com> wrote: > > > > > > I'm implementing a HT with sampling freq 2 Mhz to convert a real signal > > > > > to complex.. The required passband goes down all the way to 50 hz. > > > ... > > > > I'm afraid the bandwidth is wideband... 50 Hz all the way to 700000 Hz. > > > Whoa, Nellie!!! >
...
> > > so how long is your FIR? you *could* use halfband symmetry, but the > > 50 Hz spec on your bottom will translate to a Nyquist-50Hz spec on the > > top, which is probably better than you need. > > > tough spec.
...
> > There is no way on earth I can meet that spec using a conventional HT.
no shit. not without a lot of taps.
> If I change the passband to 10KHz to 990 KHz and have it symmetrical, > then I begin to see a decent result using approx 100 taps...which I > could implement on an FPGA.
with halfband symmetry, those 100 taps are interlaced with zero-valued taps, so the "reach" of the impulse response is about 200 taps. when you give up on symmetry, you lose those zero taps and then you have to pay for computing them. also, while this makes little difference with a DSP, in an FPGA you can take advantage of symmetry in the IR and have half (again) as many multiplications even though you still have the same number of memory accesses and additions.
> However, I need to get the lower edge of > the passband down closer to 50 Hz. Is there any other way of achieving > the same effect as a HT for baseband signals?
without bumping your signal spectrum up by (10000-50) Hz (and how're you gonna do that without an HT?) and bumping it back down, i dunno. maybe the old fashioned way we ham operators used to do it in single- sideband (SSB) with "mixers" and crystal-lattice filters. you'll need some pretty sharp IIR filters. it might not work so well. i dunno. it's a damn tough spec. r b-j