Reply by Vladimir Vassilevsky●July 4, 20092009-07-04
san_jack wrote:
>>But as per the viterbi algorithm, traverse of trace-back for 5,6 times of
>
> constraint length yields the correct decoded path. So for decoding each bit
> I should traverse minimum 5L paths.
>
>
>>san_jack wrote:
>>
>>
>>>Hi all,
>>>
>>> I have this doubt in implementation of viterbi decoder in FPGA
>>>
>>> While the trace-back unit decodes the single bit after tracing back
>
> the
>
>>>path of length 5*L, next input to the viterbi decoder should not be
>
> given.
>
>>>But if the input data is continuous, trace-back operation should be
>>>completed within single clock input period.
>>
>>Yes.
>>
>>
>>> So to fulfil the above requirement,i considered a clock for
>
> trace-back
>
>>>unit of 5*L times faster than input clock and it is working fine. Is
>
> this
>
>>>the correct way of implementing or is there an alternate
>
> implementation
>
>>>possible with using trace-back unit clock of same period as input
>
> clock.
>
>>????
>>You don't have to do the full 5L retrace. You only have to update all
>>paths by one step.
>>
>>
>>>I referred few IP cores like xilinx, Altera, Lattice,etc on this info.
>
> But
>
>>>nowhere this delay of 5*L clock cyles is specified or usage of higher
>
> clock
>
>>>frequency is mentioned.
>>
>>Vladimir Vassilevsky
>>DSP and Mixed Signal Design Consultant
>>http://www.abvolt.com
>>
Reply by san_jack●July 4, 20092009-07-04
>But as per the viterbi algorithm, traverse of trace-back for 5,6 times of
constraint length yields the correct decoded path. So for decoding each bit
I should traverse minimum 5L paths.
>
>san_jack wrote:
>
>> Hi all,
>>
>> I have this doubt in implementation of viterbi decoder in FPGA
>>
>> While the trace-back unit decodes the single bit after tracing back
the
>> path of length 5*L, next input to the viterbi decoder should not be
given.
>> But if the input data is continuous, trace-back operation should be
>> completed within single clock input period.
>
>Yes.
>
>> So to fulfil the above requirement,i considered a clock for
trace-back
>> unit of 5*L times faster than input clock and it is working fine. Is
this
>> the correct way of implementing or is there an alternate
implementation
>> possible with using trace-back unit clock of same period as input
clock.
>
>????
>You don't have to do the full 5L retrace. You only have to update all
>paths by one step.
>
>> I referred few IP cores like xilinx, Altera, Lattice,etc on this info.
But
>> nowhere this delay of 5*L clock cyles is specified or usage of higher
clock
>> frequency is mentioned.
>
>Vladimir Vassilevsky
>DSP and Mixed Signal Design Consultant
>http://www.abvolt.com
>
Reply by Vladimir Vassilevsky●July 3, 20092009-07-03
san_jack wrote:
> Hi all,
>
> I have this doubt in implementation of viterbi decoder in FPGA
>
> While the trace-back unit decodes the single bit after tracing back the
> path of length 5*L, next input to the viterbi decoder should not be given.
> But if the input data is continuous, trace-back operation should be
> completed within single clock input period.
Yes.
> So to fulfil the above requirement,i considered a clock for trace-back
> unit of 5*L times faster than input clock and it is working fine. Is this
> the correct way of implementing or is there an alternate implementation
> possible with using trace-back unit clock of same period as input clock.
????
You don't have to do the full 5L retrace. You only have to update all
paths by one step.
> I referred few IP cores like xilinx, Altera, Lattice,etc on this info. But
> nowhere this delay of 5*L clock cyles is specified or usage of higher clock
> frequency is mentioned.
Hi all,
I have this doubt in implementation of viterbi decoder in FPGA
While the trace-back unit decodes the single bit after tracing back the
path of length 5*L, next input to the viterbi decoder should not be given.
But if the input data is continuous, trace-back operation should be
completed within single clock input period.
So to fulfil the above requirement,i considered a clock for trace-back
unit of 5*L times faster than input clock and it is working fine. Is this
the correct way of implementing or is there an alternate implementation
possible with using trace-back unit clock of same period as input clock.
I referred few IP cores like xilinx, Altera, Lattice,etc on this info. But
nowhere this delay of 5*L clock cyles is specified or usage of higher clock
frequency is mentioned.