On Sep 3, 8:04=A0pm, Vladimir Vassilevsky <nos...@nowhere.com> wrote:
> KIRAN wrote:
> > Hi Guys,
>
> > I am facing some problem in using PF0 on BF531 as input.
>
> No problems in using BlackFin programmable flags.
>
> > I want
> > interrupt ( i am using channel A) to be generated when state of PF0
> > changes from Logic 0 -> Logic 1 and vice versa. =A0This is the
> > configuration iam using configuration.
> > #define RTS_INTERRUPT_CHANNEL =A0PF_A_INT
> > #define RTS_PF_NO =A00
>
> [...poorly done code snipped...]
>
Why do you think so? any justification? I am simulating CTS/RTS
handsake using PF's and using PF0 for RTS. With #defined LABELS I can
change the interrupt channel (A or B) with minimal code changes.

> Who would setup the IARs, the IVGs and IMASK and for my dear inquisitive
> friend?
>

my apologies for not providing the complete information. Once am done
with writing all the registers, I call a  function "fosHwiAdd" to
register the interrupt  provided by the Fusion RTOS . I am running my
application on Fusion RTOS. This API will sets IMASK, IAR, IVG for me.

> > With this I receive interrupt, when PF0 is high. Inside the ISR I
> > don't know how set registers to receive interrupt when PF0 state
> > changes to logic 0.
>
> Tip: if you don't know something, try reading the manual.
>
> Vladimir Vassilevsky
> DSP and Mixed Signal Design Consultanthttp://www.abvolt.com

KIRAN wrote:

> Hi Guys,
> 
> I am facing some problem in using PF0 on BF531 as input.

No problems in using BlackFin programmable flags.

> I want
> interrupt ( i am using channel A) to be generated when state of PF0
> changes from Logic 0 -> Logic 1 and vice versa.  This is the
> configuration iam using configuration.


> #define RTS_INTERRUPT_CHANNEL  PF_A_INT
> #define RTS_PF_NO  0

[...poorly done code snipped...]

Who would setup the IARs, the IVGs and IMASK and for my dear inquisitive 
friend?

> With this I receive interrupt, when PF0 is high. Inside the ISR I
> don't know how set registers to receive interrupt when PF0 state
> changes to logic 0. 

Tip: if you don't know something, try reading the manual.


Vladimir Vassilevsky
DSP and Mixed Signal Design Consultant
http://www.abvolt.com

Hi Guys,

I am facing some problem in using PF0 on BF531 as input. I want
interrupt ( i am using channel A) to be generated when state of PF0
changes from Logic 0 -> Logic 1 and vice versa.  This is the
configuration iam using configuration.

#define RTS_INTERRUPT_CHANNEL  PF_A_INT
#define RTS_PF_NO  0

#if (RTS_INTERRUPT_CHANNEL == PF_A_INT)
  #define RTS_MASK_SET_REG  FIO_MASKA_S
  #define RTS_MASK_CLR_REG  FIO_MASKA_C
  #define RTS_INTERRUPT_NUM PF_A_INT
  #define RTS_INTERRUPT_BIT  (1 << 19)
  #define RTS_MASK_DATA_REG FIO_MASKA_D
#else
  #define RTS_MASK_SET_REG  FIO_MASKB_S
  #define RTS_MASK_CLR_REG  FIO_MASKB_C
  #define RTS_INTERRUPT_NUM PF_B_INT
  #define RTS_INTERRUPT_BIT  (2 << 19)
  #define RTS_MASK_DATA_REG FIO_MASKB_D

#endif
     volatile unsigned short *mmr = NULL;
    volatile unsigned int *sic_imask = (volatile UINT32 *)SIC_IMASK;


      /* configure direction: logic 0--> input : logic 1-->output */
      mmr = (volatile UINT16 *)FIO_DIR;

      *mmr &= ~(1 << RTS_PF_NO);

      /* polarity: logic 0--> Active high: logic 1-->Active low */
      mmr = (volatile UINT16 *)FIO_POLAR;
      *mmr &= ~(1 << RTS_PF_NO);


      /* configure for level sensitive; logic 0-->level sensitive:
Logic 1-->edge sensitive */
      mmr = (volatile UINT16 *)FIO_EDGE;
      *mmr &= ~(1 << RTS_PF_NO);

     /* enable the interrupt */
      mmr = (volatile UINT16 *)RTS_MASK_SET_REG;
     *mmr = (1 << RTS_PF_NO);

     mmr = (volatile UINT16 *)RTS_MASK_CLR_REG;
     *mmr = (0 << RTS_PF_NO);


     /* let the initial state of RTS be high (MARK) */
     mmr = (volatile UINT16 *)RTS_MASK_DATA_REG;
     *mmr = (1 << RTS_PF_NO);

     mmr = (volatile UINT16 *)FIO_INEN;
     *mmr |= (1 << RTS_PF_NO);

    /* enable PF interrupt */
       *sic_imask |= RTS_INTERRUPT_BIT;

   /*************************END********************************/

With this I receive interrupt, when PF0 is high. Inside the ISR I
don't know how set registers to receive interrupt when PF0 state
changes to logic 0. Any help is appreciated.


Regards,
Kiran