Reply by sank...@hotmail.com●October 24, 20082008-10-24
Thanks Mike. it works now. The reason why the same program compiled on CCS3.1
works but not in CCS3.3 while booted from Flash was the boot loader.
CCS3.1: Does not produce any separate code section for CASE statement.
However,
CCS3.3: Does produce a separate code section (.switch) for CASE statement.
So i had to modify the bootloader to make the program works in CCS3.3.
Thanks
Sankar >I have both CCS 3.1 (DSK limited version) and CCS
Platinum 3.3 (full) installed in my computer. Current I am working on DSK6713
board.
>
>Using CCS 3.1, generated memory map (part) file looks like:
>
>TMS320C6x COFF Linker PC v5.1.0
>***************************************************************************> >
Linked Wed Oct 15 14:42:08 2008
>
>OUTPUT FILE NAME:
>ENTRY POINT SYMBOL: "_boot_start" address: 00000000
>
>MEMORY CONFIGURATION
>
> name origin length used attr fill
> ---------------------- -------- --------- -------- ---- --------
> IRAM_BOOT 00000000 00000400 00000100 RWIX
> VECTORS 00000400 00000400 00000200 RWIX
> IRAM 00000800 00037800 00030c20 RWIX
> IBUF 00038000 00008000 00000000 RWIX
> FLASH_BOOT 80000000 00000400 00000000 RWIX
> FLASH_REST 80000400 0003fc00 00013754 RWIX
>On the other hand, using CCS 3.3, generated memory map file looks like:
>
>TMS320C6x COFF Linker PC v6.0.8
>***************************************************************************> >
Linked Wed Oct 15 15:00:49 2008
>
>OUTPUT FILE NAME:
>ENTRY POINT SYMBOL: "_boot_start" address: 00000000
>
>MEMORY CONFIGURATION
> name origin length used unused attr fill
>---------------------- -------- --------- -------- -------- ---- ----
> IRAM_BOOT 00000000 00000400 00000100 00000300 RWIX
> VECTORS 00000400 00000400 00000200 00000200 RWIX
> IRAM 00000800 00037800 00030c1d 00006be3 RWIX
> IBUF 00038000 00008000 00000000 00008000 RWIX
> FLASH_BOOT 80000000 00000400 00000000 00000400 RWIX
> FLASH_REST 80000400 0003fc00 000136f5 0002c50b RWIX
>Using CCS 3.1, the application works file on DSK6713 board.
>
>However, using CCS 3.3, the following error message pops up during down loading
program into DSK6713 board (eventhough both version produces very close map
file):
>
>Loader: One or more sections of your program falls into a memory region that is
not writable. These regions will not actually be written to the target. Check
your linker configuration and/or memory map.
>
>Note1: I used the same linker configuration and the same gel file.
>Note2: The program has a boot loader in it. CCS Loader downloads the program in
SDRAM (starting @ 80000000h) from where my bootloader loads (loaded into
internal RAM) the program into internal RAM before jumping into main.
>
>Any help will be appreciated.
>
>Thanks
>
>Sankar
Reply by Michael Dunn●October 16, 20082008-10-16
Sankar,
On Thu, Oct 16, 2008 at 10:11 AM, wrote: > Hi Mike,
>
> Thanks for your clue. I disable the memory map. Now CCS 3.3 downloads the
> program and works fine. However, once i down load the code into Flash
(after
> converting into hex using hex6x and using FlashBurn version 3.11), it does
> not work. Note that the same program works once i used CCS3.1 to produce
> COFF and hex from it. I confused and do not have any idea what to suspect,
> COFF, hex6x or others.
>
> Mike as you mentioned:
>
> We haven't fixed the real problem if it loads.
>
> Would you please explain what is the real problem. As you mentioned, I
> posted the LCFile and Gel Files here.
Loader error:
An obvious problem [still not the 'real problem'] is in the GEL file
-
GEL_MapAdd(0x00000000, 0, 0x00030000, 1, 1); // Internal RAM (L2) mem
The above line is designed to have a 64k cache enabled for L2. To be
consistent with your LCF it should be:
GEL_MapAdd(0x00000000, 0, 0x00040000, 1, 1); // Internal RAM (L2) mem
- no L2 cache
hex6x/flash:
Since it looks like you simulate flash in SDRAM, the easiest way to
locate the problem would be to compare the image in SDRAM with the
image in flash.
1. Write a loop that read 1 byte from flash and 1 byte from SDRAM,
compared them [if they do not compare, increment error_cnt variable]
for all of the used locations.
2. Initialize unused mem to all 1s to simulate unused flash locations.
3. Before you start debugging, run the program once to get an idea of
how many different locations there are.
NOTE:
There could be legitimate differences in a few 'unused bytes' due
to
loader and hex6x/flash programs.
4. To start debugging, set a BP on the increment error.
mikedunn
>
> Here is my LCFile
>
> -c
> /*-stack 0xDF00*/
> -stack 0x8000
>
> MEMORY
> {
>
> IRAM_BOOT: o = 00000000h l = 00000400h
> VECTORS: o = 00000400h l = 00000400h
> IRAM: o = 00000800h l = 00037800h
> IBUF: o = 00038000h l = 00008000h
> /*SDRAM: o = 80000000h l = 01000000h*/
> FLASH_BOOT: o = 80000000h l = 00000400h
> FLASH_REST: o = 80000400h l = 0007FC00h
> }
>
> SECTIONS
> {
> /*"bootload" : LOAD = FLASH_BOOT, RUN = IRAM_BOOT*/
> "bootload" > IRAM_BOOT
>
> "vec_table": LOAD = FLASH_REST, RUN = VECTORS
> LOAD_START(_vec_ld_start), RUN_START(_vec_rn_start), SIZE(_vec_size)
> .text : LOAD = FLASH_REST, RUN = IRAM
> LOAD_START(_text_ld_start), RUN_START(_text_rn_start), SIZE(_text_size)
> .cinit : LOAD = FLASH_REST, RUN = IRAM
> LOAD_START(_cinit_ld_start), RUN_START(_cinit_rn_start), SIZE(_cinit_size)
> .const : LOAD = FLASH_REST, RUN = IRAM
> LOAD_START(_const_ld_start), RUN_START(_const_rn_start), SIZE(_const_size)
> .switch > IRAM
> .stack > IRAM
> .bss > IRAM
> .data > IRAM
> .far > IRAM
> .sysmem > IRAM
> .tables > IRAM
> .cio > IRAM
> }
>
> Here is my Gel file
>
> /*----------------------*/
> /* DSK6713.gel */
> /* Version 3.00 */
> /* */
> /* This GEL file is designed to be used in conjunction with */
> /* CCS 3.X and the TMS320C6713 based DSK. */
> /* */
> /*----------------------*/
>
> /*----------------------*/
> /* StartUp() */
> /* This function is called each time CCS is started. */
> /* Customize this function to perform desired initialization. */
> /*----------------------*/
> StartUp()
> {
> setup_memory_map();
>
> /*------------------*/
> /* Uncomment the OnTargetConnect() call for CCS 2.X */
> /* support. */
> /* */
> /* */
> /*------------------*/
> //OnTargetConnect();
> }
>
> /*----------------------*/
> /* OnTargetConnect() */
> /* This function is called by CCS when you do Debug->Connect on */
> /* CCS 3.X. When using CCS 2.X, the OnTargetConnect() call */
> /* should be uncommented from the StartUp() function. */
> /*----------------------*/
> OnTargetConnect()
> {
> /*------------------*/
> /* GEL_Reset() is used to deal with the worst case */
> /* senario of unknown target state. If for some reason */
> /* a reset is not desired upon target connection, */
> /* GEL_Reset() may be removed and replaced with */
> /* something "less brutal" like a cache initialization */
> /* function. */
> /*------------------*/
> //GEL_Reset();
>
> init_emif();
>
> GEL_TextOut("GEL StartUp Complete.\n");
> }
>
> /*----------------------*/
> /* OnReset() */
> /* This function is called by CCS when you do Debug->Resest. */
> /* The goal is to put the C6x into a known good state with */
> /* respect to cache, edma and interrupts. */
> /*----------------------*/
> OnReset( int nErrorCode )
> {
> /*------------------*/
> /* A debugger reset or GEL_Reset() does NOT reset the */
> /* C6713 pll. Uncomment the following line if you want */
> /* your pll reset. */
> /*------------------*/
> //reset_pll();
>
> init_emif();
> }
>
> /*----------------------*/
> /* OnPreFileLoaded() */
> /* This function is called automatically when the 'Load
Program'*/
> /* Menu item is selected. */
> /*----------------------*/
> OnPreFileLoaded()
> {
> /*------------------*/
> /* GEL_Reset() is used to deal with the worst case */
> /* senario of unknown target state. If for some reason */
> /* a reset is not desired upon target connection, */
> /* GEL_Reset() may be removed and replaced with */
> /* something "less brutal" like a cache initialization */
> /* function. */
> /*------------------*/
> GEL_Reset();
>
> flush_cache();
> IER = 0;
> IFR = 0;
> init_emif();
> }
>
> /*----------------------*/
> /* OnRestart() */
> /* This function is called by CCS when you do Debug->Restart. */
> /* The goal is to put the C6x into a known good state with */
> /* respect to cache, edma and interrupts. */
> /* Failure to do this can cause problems when you restart and */
> /* run your application code multiple times. This is different */
> /* then OnPreFileLoaded() which will do a GEL_Reset() to get the*/
> /* C6x into a known good state. */
> /*----------------------*/
> OnRestart(int nErrorCode )
> {
> /*------------------*/
> /* Turn off L2 for all EMIFA CE spaces. App should */
> /* manage these for coherancy in the application. */
> /* GEL_TextOut("Turn off cache segment\n"); */
> /*------------------*/
> *(int *)0x01848200 = 0; // MAR0
> *(int *)0x01848204 = 0; // MAR1
> *(int *)0x01848208 = 0; // MAR2
> *(int *)0x0184820c = 0; // MAR3
>
> /*------------------*/
> /* Disable EDMA events and interrupts and clear any */
> /* pending events. */
> /* GEL_TextOut("Disable EDMA event\n"); */
> /*------------------*/
> *(int *)0x01A0FFE8 = 0; // CIERL
> *(int *)0x01A0FFF4 = 0; // EERL
> *(int *)0x01A0FFF8 = 0xFFFFFFFF; // ECRL
>
> /* Disable other interrupts */
> IER = 0;
> IFR = 0;
> }
>
> /*----------------------*/
> /* setup_memory_map() */
> /* Memory map setup */
> /*----------------------*/
> setup_memory_map()
> {
> GEL_MapOn();
> GEL_MapReset();
>
> /* On-chip memory map */
> GEL_MapAdd(0x00000000, 0, 0x00030000, 1, 1); // Internal RAM (L2) mem
> GEL_MapAdd(0x01800000, 0, 0x00000024, 1, 1); // EMIF control regs
> GEL_MapAdd(0x01840000, 0, 0x00000004, 1, 1); // Cache configuration reg
> GEL_MapAdd(0x01844000, 0, 0x00000018, 1, 1); // L2 base addr & count regs
> GEL_MapAdd(0x01844020, 0, 0x00000018, 1, 1); // L1 base addr & count regs
> GEL_MapAdd(0x01845000, 0, 0x00000008, 1, 1); // L2 flush & clean regs
> GEL_MapAdd(0x01848200, 0, 0x00000010, 1, 1); // CE0 mem attribute regs
> GEL_MapAdd(0x01848240, 0, 0x00000010, 1, 1); // CE1 mem attribute regs
> GEL_MapAdd(0x01848280, 0, 0x00000010, 1, 1); // CE2 mem attribute regs
> GEL_MapAdd(0x018482c0, 0, 0x00000010, 1, 1); // CE3 mem attribute regs
> GEL_MapAdd(0x01880000, 0, 0x00000004, 1, 1); // HPI control reg
> GEL_MapAdd(0x018c0000, 0, 0x00000028, 1, 1); // McBSP0 regs
> GEL_MapAdd(0x01900000, 0, 0x00000028, 1, 1); // McBSP1 regs
> GEL_MapAdd(0x01940000, 0, 0x0000000c, 1, 1); // Timer0 regs
> GEL_MapAdd(0x01980000, 0, 0x0000000c, 1, 1); // Timer1 regs
> GEL_MapAdd(0x019c0000, 0, 0x0000000c, 1, 1); // Interrupt selector regs
> GEL_MapAdd(0x019c0200, 0, 0x00000004, 1, 1); // Device configuration
>
> GEL_MapAdd(0x01a00000, 0, 0x00000800, 1, 1); // EDMA parameter RAM
> GEL_MapAdd(0x01a0ff00, 0, 0x00000010, 1, 1); // EDMA event selector
> GEL_MapAdd(0x01a0ffe0, 0, 0x00000020, 1, 1); // EDMA control regs
>
> GEL_MapAdd(0x01b00000, 0, 0x00000028, 1, 1); // GPIO
> GEL_MapAdd(0x01b40000, 0, 0x0000003c, 1, 1); // I2C0
> GEL_MapAdd(0x01b44000, 0, 0x0000003c, 1, 1); // I2C1
> GEL_MapAdd(0x01b4c000, 0, 0x00000300, 1, 1); // McASP0
> GEL_MapAdd(0x01b50000, 0, 0x00000300, 1, 1); // McASP1
> GEL_MapAdd(0x01b7c000, 0, 0x00000128, 1, 1); // PLL
>
> GEL_MapAdd(0x01bc0000, 0, 0x00000050, 1, 1); // Emulation regs
> GEL_MapAdd(0x02000000, 0, 0x00000014, 0, 1); // QDMA regs
> GEL_MapAdd(0x02000020, 0, 0x00000014, 0, 1); // QDMA pseudo-regs
> GEL_MapAdd(0x30000000, 0, 0x04000000, 1, 1); // McBSP0 data
> GEL_MapAdd(0x34000000, 0, 0x04000000, 1, 1); // McBSP1 data
>
> GEL_MapAdd(0x3c000000, 0, 0x00010000, 1, 1); // McASP0 data
> GEL_MapAdd(0x3c100000, 0, 0x00010000, 1, 1); // McASP1 data
>
> /* Off-chip memory map */
> GEL_MapAdd(0x80000000, 0, 0x01000000, 1, 1); // CE0, SDRAM, 16 MBytes
> GEL_MapAdd(0x90000000, 0, 0x00080000, 1, 1); // CE1, 8-bit ROM, 128KBytes
> GEL_MapAdd(0x90080000, 0, 0x00000008, 1, 1); // CE1, 8-bit I/O port
> GEL_MapAdd(0xA0000000, 0, 0x10000000, 1, 1); // CE2 - Daughtercard
> GEL_MapAdd(0xB0000000, 0, 0x10000000, 1, 1); // CE3 - Daughtercard
> }
>
> /*----------------------*/
> /* clear_memory_map() */
> /* Memory map disable */
> /*----------------------*/
> clear_memory_map()
> {
> GEL_MapOff();
> }
>
> /*----------------------*/
> /* CPLD DEFINITIONS */
> /*----------------------*/
> #define CPLD_STAT 0x90080000
> #define CPLD_DC 0x90080001
> #define CPLD_REV 0x90080004
> #define CPLD_MISC 0x90080006
>
> #define Get_Board_Rev ((*(char *)CPLD_REV) & 0x07)
> #define Get_Cpld_Rev ((*(char *)CPLD_REV>>4) & 0x0F)
> #define Get_Switches ((*(char *)CPLD_STAT>>4) & 0x0F)
>
> #define LED0_on *(char *)CPLD_STAT = 0x01
> #define LED1_on *(char *)CPLD_STAT = 0x02
> #define LED2_on *(char *)CPLD_STAT = 0x04
> #define LED3_on *(char *)CPLD_STAT = 0x08
> #define LEDs_off *(char *)CPLD_STAT = 0x00
>
> /*----------------------*/
> /* init_emif() */
> /* Emif initialization */
> /*----------------------*/
> init_emif()
> {
> #define EMIF_GCTL 0x01800000
> #define EMIF_CE1 0x01800004
> #define EMIF_CE0 0x01800008
> #define EMIF_CE2 0x01800010
> #define EMIF_CE3 0x01800014
> #define EMIF_SDRAMCTL 0x01800018
> #define EMIF_SDRAMTIM 0x0180001C
> #define EMIF_SDRAMEXT 0x01800020
> #define EMIF_CCFG 0x01840000; // Cache configuration register
>
> /* EMIF setup */
> *(int *)EMIF_GCTL = 0x00000068;
> *(int *)EMIF_CE0 = 0xffffbf33; // CE0 SDRAM
> *(int *)EMIF_CE1 = 0x02208802; // CE1 Flash 8-bit
> *(int *)EMIF_CE2 = 0x22a28a22; // CE2 Daughtercard 32-bit async
> *(int *)EMIF_CE3 = 0x22a28a22; // CE3 Daughtercard 32-bit async
>
> if (Get_Board_Rev == 2)
> {
> *(int *)EMIF_SDRAMCTL = 0x57115000; // SDRAM control (16 Mb)
> }
> else
> {
> *(int *)EMIF_SDRAMCTL = 0x47115000; // SDRAM control (8 Mb)
> }
> *(int *)EMIF_SDRAMTIM = 0x00000578; // SDRAM timing (refresh)
> *(int *)EMIF_SDRAMEXT = 0x000a8529; // SDRAM Extension register
> }
>
> /*----------------------*/
> /* flush_cache() */
> /* Flush L1 & L2 cache */
> /*----------------------*/
> flush_cache()
> {
> /* Invalidate L1P and L1D */
> *(int *)0x01840000 = (*(int *)0x01840000 | 0x00000300);
>
> /* Clean L2 */
> *(int *)0x01845004 = 0x1;
> }
>
> /*----------------------*/
> /* init_cpld() */
> /* CPLD Initialization */
> /*----------------------*/
> init_cpld()
> {
> *(char*)CPLD_STAT = 0;
> *(char*)CPLD_DC = 0;
> *(char*)CPLD_MISC = 0;
> }
>
> /*----------------------*/
> /* C6713 PLL SUPPORT */
> /*----------------------*/
> #define PLL_BASE_ADDR 0x01b7c000
> #define PLL_PID ( PLL_BASE_ADDR + 0x000 )
> #define PLL_CSR ( PLL_BASE_ADDR + 0x100 )
> #define PLL_MULT ( PLL_BASE_ADDR + 0x110 )
> #define PLL_DIV0 ( PLL_BASE_ADDR + 0x114 )
> #define PLL_DIV1 ( PLL_BASE_ADDR + 0x118 )
> #define PLL_DIV2 ( PLL_BASE_ADDR + 0x11C )
> #define PLL_DIV3 ( PLL_BASE_ADDR + 0x120 )
> #define PLL_OSCDIV1 ( PLL_BASE_ADDR + 0x124 )
>
> #define CSR_PLLEN 0x00000001
> #define CSR_PLLPWRDN 0x00000002
> #define CSR_PLLRST 0x00000008
> #define CSR_PLLSTABLE 0x00000040
> #define DIV_ENABLE 0x00008000
>
> /*----------------------*/
> /* reset_pll() */
> /* Pll Reset */
> /*----------------------*/
> reset_pll()
> {
> /* Set the PLL back to power on reset state*/
> *(int *)PLL_CSR = 0x00000048;
> *(int *)PLL_DIV3 = 0x00008001;
> *(int *)PLL_DIV2 = 0x00008001;
> *(int *)PLL_DIV1 = 0x00008000;
> *(int *)PLL_DIV0 = 0x00008000;
> *(int *)PLL_MULT = 0x00000007;
> *(int *)PLL_MULT = 0x00000007;
> *(int *)PLL_OSCDIV1 = 0x00008007;
> }
>
> /*----------------------*/
> /* init_pll() */
> /* Pll Initialization */
> /*----------------------*/
> init_pll()
> {
> /*------------------*/
> /* When PLLEN is off DSP is running with CLKIN clock */
> /* source, currently 50MHz or 20ns clk rate. */
> /*------------------*/
> *(int *)PLL_CSR &= ~CSR_PLLEN;
>
> /* Reset the pll. PLL takes 125ns to reset. */
> *(int *)PLL_CSR |= CSR_PLLRST;
>
> /*------------------*/
> /* PLLOUT = CLKIN/(DIV0+1) * PLLM */
> /* 450 = 50/1 * 9 */
> /*------------------*/
> *(int *)PLL_DIV0 = DIV_ENABLE + 0;
> *(int *)PLL_MULT = 9;
> *(int *)PLL_OSCDIV1 = DIV_ENABLE + 4;
>
> /*------------------*/
> /* Program in reverse order. */
> /* DSP requires that pheriheral clocks be less then */
> /* 1/2 the CPU clock at all times. */
> /*------------------*/
> *(int *)PLL_DIV3 = DIV_ENABLE + 4;
> *(int *)PLL_DIV2 = DIV_ENABLE + 3;
> *(int *)PLL_DIV1 = DIV_ENABLE + 1;
> *(int *)PLL_CSR &= ~CSR_PLLRST;
>
> /*------------------*/
> /* Now enable pll path and we are off and running at */
> /* 225MHz with 90 MHz SDRAM. */
> /*------------------*/
> *(int *)PLL_CSR |= CSR_PLLEN;
> }
>
> /*----------------------*/
> /* DSK6713 MENU */
> /*----------------------*/
> menuitem "DSK6713 Functions";
>
> hotmenu Reset()
> {
> GEL_Reset( );
> }
>
> hotmenu InitEmif()
> {
> init_emif();
> }
>
> hotmenu InitPll()
> {
> init_pll();
> }
>
> hotmenu InitCpld()
> {
> init_cpld();
> }
>
> /*----------------------*/
> /* RESET MENU */
> /*----------------------*/
> menuitem "Resets";
>
> hotmenu ClearBreakPts_Reset_EMIFset()
> {
> GEL_BreakPtReset();
> GEL_Reset();
> init_emif();
> }
>
> hotmenu FlushCache()
> {
> flush_cache();
> }
>
> hotmenu ResetPll()
> {
> reset_pll();
> }
>
> /*----------------------*/
> /* MEMORY MAP MENU */
> /*----------------------*/
> menuitem "Memory Map";
>
> hotmenu SetMemoryMap()
> {
> setup_memory_map();
> }
>
> hotmenu ClearMemoryMap()
> {
> clear_memory_map();
> }
>
> /*----------------------*/
> /* LED_cycle() */
> /*----------------------*/
> LED_cycle()
> {
> LED3_on;
> LED2_on;
> LED1_on;
> LED2_on;
> LED3_on;
> LEDs_off;
> }
>
> /*----------------------*/
> /* Check DSK MENU */
> /*----------------------*/
> menuitem "Check DSK";
> hotmenu QuickTest()
> {
> LED_cycle();
> LED_cycle();
> LED_cycle();
> GEL_TextOut(" Switches: %d Board Revision: %d CPLD Revision: %d\n\n",
> "DSKOutput", 1, 1, 1, Get_Switches, Get_Board_Rev, Get_Cpld_Rev);
>
> }
>
> Sankar
>
>>I have both CCS 3.1 (DSK limited version) and CCS Platinum 3.3 (full)
>> installed in my computer. Current I am working on DSK6713 board.
>>
>>Using CCS 3.1, generated memory map (part) file looks like:
>>
>>TMS320C6x COFF Linker PC v5.1.0
>>***************************************************************************>
>> > Linked Wed Oct 15 14:42:08 2008
>>
>>OUTPUT FILE NAME:
>>ENTRY POINT SYMBOL: "_boot_start" address: 00000000
>>
>>MEMORY CONFIGURATION
>>
>> name origin length used attr fill
>> ---------------------- -------- --------- -------- ---- --------
>> IRAM_BOOT 00000000 00000400 00000100 RWIX
>> VECTORS 00000400 00000400 00000200 RWIX
>> IRAM 00000800 00037800 00030c20 RWIX
>> IBUF 00038000 00008000 00000000 RWIX
>> FLASH_BOOT 80000000 00000400 00000000 RWIX
>> FLASH_REST 80000400 0003fc00 00013754 RWIX
>>On the other hand, using CCS 3.3, generated memory map file looks like:
>>
>>TMS320C6x COFF Linker PC v6.0.8
>>***************************************************************************>
>> > Linked Wed Oct 15 15:00:49 2008
>>
>>OUTPUT FILE NAME:
>>ENTRY POINT SYMBOL: "_boot_start" address: 00000000
>>
>>MEMORY CONFIGURATION
>> name origin length used unused attr fill
>>---------------------- -------- --------- -------- -------- ---- ----
>> IRAM_BOOT 00000000 00000400 00000100 00000300 RWIX
>> VECTORS 00000400 00000400 00000200 00000200 RWIX
>> IRAM 00000800 00037800 00030c1d 00006be3 RWIX
>> IBUF 00038000 00008000 00000000 00008000 RWIX
>> FLASH_BOOT 80000000 00000400 00000000 00000400 RWIX
>> FLASH_REST 80000400 0003fc00 000136f5 0002c50b RWIX
>>Using CCS 3.1, the application works file on DSK6713 board.
>>
>>However, using CCS 3.3, the following error message pops up during down
>> loading program into DSK6713 board (eventhough both version produces very
>> close map file):
>>
>>Loader: One or more sections of your program falls into a memory region
>> that is not writable. These regions will not actually be written to the
>> target. Check your linker configuration and/or memory map.
>>
>>Note1: I used the same linker configuration and the same gel file.
>>Note2: The program has a boot loader in it. CCS Loader downloads the
>> program in SDRAM (starting @ 80000000h) from where my bootloader loads
>> (loaded into internal RAM) the program into internal RAM before jumping
into
>> main.
>>
>>Any help will be appreciated.
>>
>>Thanks
>>
>>Sankar
>
>>
> --
www.dsprelated.com/blogs-1/nf/Mike_Dunn.php
Reply by sank...@hotmail.com●October 16, 20082008-10-16
Hi Mike,
Thanks for your clue. I disable the memory map. Now CCS 3.3 downloads the
program and works fine. However, once i down load the code into Flash (after
converting into hex using hex6x and using FlashBurn version 3.11), it does not
work. Note that the same program works once i used CCS3.1 to produce COFF and
hex from it. I confused and do not have any idea what to suspect, COFF, hex6x or
others.
Mike as you mentioned:
We haven't fixed the real problem if it loads.
Would you please explain what is the real problem. As you mentioned, I posted
the LCFile and Gel Files here.
Here is my LCFile
-c
/*-stack 0xDF00*/
-stack 0x8000
MEMORY
{
IRAM_BOOT: o = 00000000h l = 00000400h
VECTORS: o = 00000400h l = 00000400h
IRAM: o = 00000800h l = 00037800h
IBUF: o = 00038000h l = 00008000h
/*SDRAM: o = 80000000h l = 01000000h*/
FLASH_BOOT: o = 80000000h l = 00000400h
FLASH_REST: o = 80000400h l = 0007FC00h
}
SECTIONS
{
/*"bootload" : LOAD = FLASH_BOOT, RUN = IRAM_BOOT*/
"bootload" > IRAM_BOOT
.switch > IRAM
.stack > IRAM
.bss > IRAM
.data > IRAM
.far > IRAM
.sysmem > IRAM
.tables > IRAM
.cio > IRAM
}
Here is my Gel file
/*--------------------------*/
/* DSK6713.gel */
/* Version 3.00 */
/* */
/* This GEL file is designed to be used in conjunction with */
/* CCS 3.X and the TMS320C6713 based DSK. */
/* */
/*--------------------------*/
/*--------------------------*/
/* StartUp() */
/* This function is called each time CCS is started. */
/* Customize this function to perform desired initialization. */
/*--------------------------*/
StartUp()
{
setup_memory_map();
/*------------------*/
/* Uncomment the OnTargetConnect() call for CCS 2.X */
/* support. */
/* */
/* */
/*------------------*/
//OnTargetConnect();
}
/*--------------------------*/
/* OnTargetConnect() */
/* This function is called by CCS when you do Debug->Connect on */
/* CCS 3.X. When using CCS 2.X, the OnTargetConnect() call */
/* should be uncommented from the StartUp() function. */
/*--------------------------*/
OnTargetConnect()
{
/*------------------*/
/* GEL_Reset() is used to deal with the worst case */
/* senario of unknown target state. If for some reason */
/* a reset is not desired upon target connection, */
/* GEL_Reset() may be removed and replaced with */
/* something "less brutal" like a cache initialization */
/* function. */
/*------------------*/
//GEL_Reset();
init_emif();
GEL_TextOut("GEL StartUp Complete.\n");
}
/*--------------------------*/
/* OnReset() */
/* This function is called by CCS when you do Debug->Resest. */
/* The goal is to put the C6x into a known good state with */
/* respect to cache, edma and interrupts. */
/*--------------------------*/
OnReset( int nErrorCode )
{
/*------------------*/
/* A debugger reset or GEL_Reset() does NOT reset the */
/* C6713 pll. Uncomment the following line if you want */
/* your pll reset. */
/*------------------*/
//reset_pll();
init_emif();
}
/*--------------------------*/
/* OnPreFileLoaded() */
/* This function is called automatically when the 'Load Program'*/
/* Menu item is selected. */
/*--------------------------*/
OnPreFileLoaded()
{
/*------------------*/
/* GEL_Reset() is used to deal with the worst case */
/* senario of unknown target state. If for some reason */
/* a reset is not desired upon target connection, */
/* GEL_Reset() may be removed and replaced with */
/* something "less brutal" like a cache initialization */
/* function. */
/*------------------*/
GEL_Reset();
flush_cache();
IER = 0;
IFR = 0;
init_emif();
}
/*--------------------------*/
/* OnRestart() */
/* This function is called by CCS when you do Debug->Restart. */
/* The goal is to put the C6x into a known good state with */
/* respect to cache, edma and interrupts. */
/* Failure to do this can cause problems when you restart and */
/* run your application code multiple times. This is different */
/* then OnPreFileLoaded() which will do a GEL_Reset() to get the*/
/* C6x into a known good state. */
/*--------------------------*/
OnRestart(int nErrorCode )
{
/*------------------*/
/* Turn off L2 for all EMIFA CE spaces. App should */
/* manage these for coherancy in the application. */
/* GEL_TextOut("Turn off cache segment\n"); */
/*------------------*/
*(int *)0x01848200 = 0; // MAR0
*(int *)0x01848204 = 0; // MAR1
*(int *)0x01848208 = 0; // MAR2
*(int *)0x0184820c = 0; // MAR3
/*------------------*/
/* Program in reverse order. */
/* DSP requires that pheriheral clocks be less then */
/* 1/2 the CPU clock at all times. */
/*------------------*/
*(int *)PLL_DIV3 = DIV_ENABLE + 4;
*(int *)PLL_DIV2 = DIV_ENABLE + 3;
*(int *)PLL_DIV1 = DIV_ENABLE + 1;
*(int *)PLL_CSR &= ~CSR_PLLRST;
/*------------------*/
/* Now enable pll path and we are off and running at */
/* 225MHz with 90 MHz SDRAM. */
/*------------------*/
*(int *)PLL_CSR |= CSR_PLLEN;
}
/*--------------------------*/
/* DSK6713 MENU */
/*--------------------------*/
menuitem "DSK6713 Functions";
hotmenu Reset()
{
GEL_Reset( );
}
hotmenu InitEmif()
{
init_emif();
}
hotmenu InitPll()
{
init_pll();
}
hotmenu InitCpld()
{
init_cpld();
}
/*--------------------------*/
/* RESET MENU */
/*--------------------------*/
menuitem "Resets";
Sankar >I have both CCS 3.1 (DSK limited version) and CCS
Platinum 3.3 (full) installed in my computer. Current I am working on DSK6713
board.
>
>Using CCS 3.1, generated memory map (part) file looks like:
>
>TMS320C6x COFF Linker PC v5.1.0
>***************************************************************************> >
Linked Wed Oct 15 14:42:08 2008
>
>OUTPUT FILE NAME:
>ENTRY POINT SYMBOL: "_boot_start" address: 00000000
>
>MEMORY CONFIGURATION
>
> name origin length used attr fill
> ---------------------- -------- --------- -------- ---- --------
> IRAM_BOOT 00000000 00000400 00000100 RWIX
> VECTORS 00000400 00000400 00000200 RWIX
> IRAM 00000800 00037800 00030c20 RWIX
> IBUF 00038000 00008000 00000000 RWIX
> FLASH_BOOT 80000000 00000400 00000000 RWIX
> FLASH_REST 80000400 0003fc00 00013754 RWIX
>On the other hand, using CCS 3.3, generated memory map file looks like:
>
>TMS320C6x COFF Linker PC v6.0.8
>***************************************************************************> >
Linked Wed Oct 15 15:00:49 2008
>
>OUTPUT FILE NAME:
>ENTRY POINT SYMBOL: "_boot_start" address: 00000000
>
>MEMORY CONFIGURATION
> name origin length used unused attr fill
>---------------------- -------- --------- -------- -------- ---- ----
> IRAM_BOOT 00000000 00000400 00000100 00000300 RWIX
> VECTORS 00000400 00000400 00000200 00000200 RWIX
> IRAM 00000800 00037800 00030c1d 00006be3 RWIX
> IBUF 00038000 00008000 00000000 00008000 RWIX
> FLASH_BOOT 80000000 00000400 00000000 00000400 RWIX
> FLASH_REST 80000400 0003fc00 000136f5 0002c50b RWIX
>Using CCS 3.1, the application works file on DSK6713 board.
>
>However, using CCS 3.3, the following error message pops up during down loading
program into DSK6713 board (eventhough both version produces very close map
file):
>
>Loader: One or more sections of your program falls into a memory region that is
not writable. These regions will not actually be written to the target. Check
your linker configuration and/or memory map.
>
>Note1: I used the same linker configuration and the same gel file.
>Note2: The program has a boot loader in it. CCS Loader downloads the program in
SDRAM (starting @ 80000000h) from where my bootloader loads (loaded into
internal RAM) the program into internal RAM before jumping into main.
>
>Any help will be appreciated.
>
>Thanks
>
>Sankar
Reply by Michael Dunn●October 15, 20082008-10-15
Sankar,
On Wed, Oct 15, 2008 at 4:44 PM, wrote: >
> Thanks a lot Mike.
>
> 1. I did not install any service release yet.
>
> 2. As you mentioned I have to handle the interrupt vector table location in
> Boot code. I did set the vector address at 0400 during initialization of
> DSP. I did not do it in Boot Code. Do you think it would be a problem.
>
> 3. I am not aware of LCFile. Would you please explain what it is.
LCF = "linker Command File" >
> I talked to TI SUPPORT today. They told me that the problem I am having is
a
> known issue. But they did not get me back yet.
I suspect that the fix is either a TI service release or a DSK
update from SD.
mikedunn >
> Thank you again Mike for your support.
>
> Sankar
>
>>I have both CCS 3.1 (DSK limited version) and CCS Platinum 3.3 (full)
>> installed in my computer. Current I am working on DSK6713 board.
>>
>>Using CCS 3.1, generated memory map (part) file looks like:
>>
>>TMS320C6x COFF Linker PC v5.1.0
>>***************************************************************************>
>> > Linked Wed Oct 15 14:42:08 2008
>>
>>OUTPUT FILE NAME:
>>ENTRY POINT SYMBOL: "_boot_start" address: 00000000
>>
>>MEMORY CONFIGURATION
>>
>> name origin length used attr fill
>> ---------------------- -------- --------- -------- ---- --------
>> IRAM_BOOT 00000000 00000400 00000100 RWIX
>> VECTORS 00000400 00000400 00000200 RWIX
>> IRAM 00000800 00037800 00030c20 RWIX
>> IBUF 00038000 00008000 00000000 RWIX
>> FLASH_BOOT 80000000 00000400 00000000 RWIX
>> FLASH_REST 80000400 0003fc00 00013754 RWIX
>>On the other hand, using CCS 3.3, generated memory map file looks like:
>>
>>TMS320C6x COFF Linker PC v6.0.8
>>***************************************************************************>
>> > Linked Wed Oct 15 15:00:49 2008
>>
>>OUTPUT FILE NAME:
>>ENTRY POINT SYMBOL: "_boot_start" address: 00000000
>>
>>MEMORY CONFIGURATION
>> name origin length used unused attr fill
>>---------------------- -------- --------- -------- -------- ---- ----
>> IRAM_BOOT 00000000 00000400 00000100 00000300 RWIX
>> VECTORS 00000400 00000400 00000200 00000200 RWIX
>> IRAM 00000800 00037800 00030c1d 00006be3 RWIX
>> IBUF 00038000 00008000 00000000 00008000 RWIX
>> FLASH_BOOT 80000000 00000400 00000000 00000400 RWIX
>> FLASH_REST 80000400 0003fc00 000136f5 0002c50b RWIX
>>Using CCS 3.1, the application works file on DSK6713 board.
>>
>>However, using CCS 3.3, the following error message pops up during down
>> loading program into DSK6713 board (eventhough both version produces very
>> close map file):
>>
>>Loader: One or more sections of your program falls into a memory region
>> that is not writable. These regions will not actually be written to the
>> target. Check your linker configuration and/or memory map.
>>
>>Note1: I used the same linker configuration and the same gel file.
>>Note2: The program has a boot loader in it. CCS Loader downloads the
>> program in SDRAM (starting @ 80000000h) from where my bootloader loads
>> (loaded into internal RAM) the program into internal RAM before jumping
into
>> main.
>>
>>Any help will be appreciated.
>>
>>Thanks
>>
>>Sankar
>
>>
> --
www.dsprelated.com/blogs-1/nf/Mike_Dunn.php
Reply by sank...@hotmail.com●October 15, 20082008-10-15
Thanks a lot Mike.
1. I did not install any service release yet.
2. As you mentioned I have to handle the interrupt vector table location in Boot
code. I did set the vector address at 0400 during initialization of DSP. I did
not do it in Boot Code. Do you think it would be a problem.
3. I am not aware of LCFile. Would you please explain what it is.
I talked to TI SUPPORT today. They told me that the problem I am having is a
known issue. But they did not get me back yet.
Thank you again Mike for your support.
Sankar
>I have both CCS 3.1 (DSK limited version) and CCS
Platinum 3.3 (full) installed in my computer. Current I am working on DSK6713
board.
>
>Using CCS 3.1, generated memory map (part) file looks like:
>
>TMS320C6x COFF Linker PC v5.1.0
>***************************************************************************> >
Linked Wed Oct 15 14:42:08 2008
>
>OUTPUT FILE NAME:
>ENTRY POINT SYMBOL: "_boot_start" address: 00000000
>
>MEMORY CONFIGURATION
>
> name origin length used attr fill
> ---------------------- -------- --------- -------- ---- --------
> IRAM_BOOT 00000000 00000400 00000100 RWIX
> VECTORS 00000400 00000400 00000200 RWIX
> IRAM 00000800 00037800 00030c20 RWIX
> IBUF 00038000 00008000 00000000 RWIX
> FLASH_BOOT 80000000 00000400 00000000 RWIX
> FLASH_REST 80000400 0003fc00 00013754 RWIX
>On the other hand, using CCS 3.3, generated memory map file looks like:
>
>TMS320C6x COFF Linker PC v6.0.8
>***************************************************************************> >
Linked Wed Oct 15 15:00:49 2008
>
>OUTPUT FILE NAME:
>ENTRY POINT SYMBOL: "_boot_start" address: 00000000
>
>MEMORY CONFIGURATION
> name origin length used unused attr fill
>---------------------- -------- --------- -------- -------- ---- ----
> IRAM_BOOT 00000000 00000400 00000100 00000300 RWIX
> VECTORS 00000400 00000400 00000200 00000200 RWIX
> IRAM 00000800 00037800 00030c1d 00006be3 RWIX
> IBUF 00038000 00008000 00000000 00008000 RWIX
> FLASH_BOOT 80000000 00000400 00000000 00000400 RWIX
> FLASH_REST 80000400 0003fc00 000136f5 0002c50b RWIX
>Using CCS 3.1, the application works file on DSK6713 board.
>
>However, using CCS 3.3, the following error message pops up during down loading
program into DSK6713 board (eventhough both version produces very close map
file):
>
>Loader: One or more sections of your program falls into a memory region that is
not writable. These regions will not actually be written to the target. Check
your linker configuration and/or memory map.
>
>Note1: I used the same linker configuration and the same gel file.
>Note2: The program has a boot loader in it. CCS Loader downloads the program in
SDRAM (starting @ 80000000h) from where my bootloader loads (loaded into
internal RAM) the program into internal RAM before jumping into main.
>
>Any help will be appreciated.
>
>Thanks
>
>Sankar
Reply by Michael Dunn●October 15, 20082008-10-15
Sankar,
On Wed, Oct 15, 2008 at 2:44 PM, wrote: >
> I have both CCS 3.1 (DSK limited version) and CCS Platinum 3.3 (full)
> installed in my computer. Current I am working on DSK6713 board.
Hopefully you have installed at least 1 of the service releases [It is
probably not relevant, but there has been several updates since the CD
was released]. >
> Using CCS 3.1, generated memory map (part) file looks like:
>
> TMS320C6x COFF Linker PC v5.1.0
>
***************************************************************************>>
> Linked Wed Oct 15 14:42:08 2008
>
> OUTPUT FILE NAME: <./Debug/my_NeuroMedic_Boot_Int_0r1.out>
> ENTRY POINT SYMBOL: "_boot_start" address: 00000000
>
> MEMORY CONFIGURATION
>
> name origin length used attr fill
> ---------------------- -------- --------- -------- ---- --------
> IRAM_BOOT 00000000 00000400 00000100 RWIX
> VECTORS 00000400 00000400 00000200 RWIX
> IRAM 00000800 00037800 00030c20 RWIX
> IBUF 00038000 00008000 00000000 RWIX
> FLASH_BOOT 80000000 00000400 00000000 RWIX
> FLASH_REST 80000400 0003fc00 00013754 RWIX
>
> On the other hand, using CCS 3.3, generated memory map file looks like:
>
> TMS320C6x COFF Linker PC v6.0.8
>
***************************************************************************>>
> Linked Wed Oct 15 15:00:49 2008
>
> OUTPUT FILE NAME: <./Debug/myNeuroMedic_Boot_Int_Emu_0r1.out>
> ENTRY POINT SYMBOL: "_boot_start" address: 00000000
>
> MEMORY CONFIGURATION
> name origin length used unused attr fill
> ---------------------- -------- --------- -------- -------- ---- ----
> IRAM_BOOT 00000000 00000400 00000100 00000300 RWIX
> VECTORS 00000400 00000400 00000200 00000200 RWIX
> IRAM 00000800 00037800 00030c1d 00006be3 RWIX
> IBUF 00038000 00008000 00000000 00008000 RWIX
> FLASH_BOOT 80000000 00000400 00000000 00000400 RWIX
> FLASH_REST 80000400 0003fc00 000136f5 0002c50b RWIX
>
> Using CCS 3.1, the application works file on DSK6713 board.
FYI.
With the default setup, your interrupt vector table [as known to the
DSP] is 0 based and not 0x400 based. You will need to handle it in
your boot code [or never use interrupts]. >
> However, using CCS 3.3, the following error message pops up during down
> loading program into DSK6713 board (eventhough both version produces very
> close map file):
>
> Loader: One or more sections of your program falls into a memory region
that
> is not writable. These regions will not actually be written to the target.
> Check your linker configuration and/or memory map.
It was really nice to CCS to carefully NOT tell you what address it
had the problem with :-)
Your problem is with the memory map [CCS menu - Option->MemoryMap]
possibly in interaction with the GEL file or LCFile.
To verify my theory:
1. bringup CCS and connect to the DSK.
2. look at the memory map [Option->MemoryMap]. I predict that it will
be enabled.
3. uncheck the 'memory map enabled' checkbox and load your program.
I
predict that it will load.
4. you haven't fixed the real problem if it loads. post your LCFile
and GEL file to 'get some eyes on them'. maybe we will locate the
problem.
mikedunn >
> Note1: I used the same linker configuration and the same gel file.
> Note2: The program has a boot loader in it. CCS Loader downloads the
program
> in SDRAM (starting @ 80000000h) from where my bootloader loads (loaded into
> internal RAM) the program into internal RAM before jumping into main.
>
> Any help will be appreciated.
>
> Thanks
>
> Sankar
--
www.dsprelated.com/blogs-1/nf/Mike_Dunn.php
Reply by sank...@hotmail.com●October 15, 20082008-10-15
I have both CCS 3.1 (DSK limited version) and CCS Platinum 3.3 (full) installed
in my computer. Current I am working on DSK6713 board.
Using CCS 3.1, generated memory map (part) file looks like:
TMS320C6x COFF Linker PC v5.1.0
***************************************************************************>>
Linked Wed Oct 15 14:42:08 2008
OUTPUT FILE NAME: <./Debug/my_NeuroMedic_Boot_Int_0r1.out>
ENTRY POINT SYMBOL: "_boot_start" address: 00000000
MEMORY CONFIGURATION
name origin length used attr fill
---------------------- -------- --------- -------- ---- --------
IRAM_BOOT 00000000 00000400 00000100 RWIX
VECTORS 00000400 00000400 00000200 RWIX
IRAM 00000800 00037800 00030c20 RWIX
IBUF 00038000 00008000 00000000 RWIX
FLASH_BOOT 80000000 00000400 00000000 RWIX
FLASH_REST 80000400 0003fc00 00013754 RWIX
On the other hand, using CCS 3.3, generated memory map file looks like:
TMS320C6x COFF Linker PC v6.0.8
***************************************************************************>>
Linked Wed Oct 15 15:00:49 2008
OUTPUT FILE NAME: <./Debug/myNeuroMedic_Boot_Int_Emu_0r1.out>
ENTRY POINT SYMBOL: "_boot_start" address: 00000000
MEMORY CONFIGURATION
name origin length used unused attr fill
---------------------- -------- --------- -------- -------- ---- ----
IRAM_BOOT 00000000 00000400 00000100 00000300 RWIX
VECTORS 00000400 00000400 00000200 00000200 RWIX
IRAM 00000800 00037800 00030c1d 00006be3 RWIX
IBUF 00038000 00008000 00000000 00008000 RWIX
FLASH_BOOT 80000000 00000400 00000000 00000400 RWIX
FLASH_REST 80000400 0003fc00 000136f5 0002c50b RWIX
Using CCS 3.1, the application works file on DSK6713 board.
However, using CCS 3.3, the following error message pops up during down loading
program into DSK6713 board (eventhough both version produces very close map
file):
Loader: One or more sections of your program falls into a memory region that is
not writable. These regions will not actually be written to the target. Check
your linker configuration and/or memory map.
Note1: I used the same linker configuration and the same gel file.
Note2: The program has a boot loader in it. CCS Loader downloads the program in
SDRAM (starting @ 80000000h) from where my bootloader loads (loaded into
internal RAM) the program into internal RAM before jumping into main.