We use 21161 for our project. and VisualDSP++ 2.0
We encountered a strange situation in one of our code files
When we compile the code with the -Os switch, the compiler produces a code
which
tries to utilise the SIMD(Single Instruction Multiple data) feature in the
21161
processor. This code works in some cases and does not work in some other
cases.
The following example does not work properly.
static void xyz (
float *InReal, /* in, Real part of FFT */
float *InImag, /* in, Imaginary part of FFT */
float *Output ) /* out, Spectre de puissance */
{
int i; /* needs to be volatile to stop optimizer using the SIMD feture or
-no-simd compiler option has to be used */
/* Calcul de la raie 0 */
Output[0] = InReal[0]*InReal[0];
/* Calcul du spectre de puissance */
for (i=1; i<8; i++)
{
Output[i] = InReal[i]*InReal[i] + InImag[i]*InImag[i];
}
}
and a call to this function with sample data does not prodece expected data.
float InReal[8] =
{
0,1.11,2.22,3.33,4.44,5.55,6.66,7.77
};
float InImag[8] =
{
0,1.11,2.22,3.33,4.44,5.55,6.66,7.77
};
float Output[8];
xyz(InReal,InImag,Output);
In the above example, the code in the "for" loop was optimised to
utilise the
SIMD feature of the processor. The assembler code looks like
bit set mode1 0x200000; nop;
m4=2;
-- bubble --
r2=dm(i4,m4);
F2F2, r12=dm(i0,m4);
lcntr=3, do(pc,.P2L4-1)until lce;
.
F12*F12, r8=dm(i4,m4);
F2F12, r12=dm(i0,m4);
F2F8, dm(i1,2)=r2;
//end loop .P2L3;
.P2L4:
bit clr mode1 0x200000; nop;
Though the PEYEN bit is set in the MODE1 Register, the code does not seem to
work as expected.
The computations inside the "for" loop are supposed to be performed in
parallel
in the two processing elements (PEx and PEy) with different sets of data.
This
situation was simulated in the VDSP simulator and it produces the expected
result. When it was tried in the emulator, only onset of computations (the
explicit ones on the PEx) seem to be performed and the computations on the
implicit registers, PEy, seems to contain zeros. And hence only the alternate
elements in the "Output" array get meaningful data and the remaining
entries
contain zeros.
Any suggestions? Is there any thing else we need to take care to enable SIMD
mode apart from the MODE1 register?
Thanks,
Kannan,
Contract Engineer,
TRW Automotive Electronics,
Cirencester,
UK Gl7 1EN
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