Rohit,

It the end, your project will have to perform any initialization in the startup code and will not have a 'gel' available to use. So your better off writing the initialization your self rather than using a Gel file.

Are you saying you lose connection between CCS and the target DSP or between the target DSP and the FPGA?

Have you tried debugging/single stepping the Gel file to determine exactly what line causes the problem?
(you can past the gel file into the script window to debug it.)

R. Williams

---------- Original Message -----------
From: r...@gmail.com
To: c...
Sent: Thu, 08 Apr 2010 15:12:37 -0400
Subject: [c6x] DSP EMIF

>
>
> Hi
> I have a custom board with a C6000 DSP and FPGA , using EMIF to connect both . But whenever I initialize the EMIF in the GEL , I loose connection to the board . Without the initialization it works fine .
>
> Rohit

Rohit-

I noticed Mike's post... I meant ARDY, not HRDY. Sorry.

-Jeff

>> I have a custom board with a C6000 DSP and FPGA , using
>> EMIF to connect both . But whenever I initialize the EMIF
>> in the GEL , I loose connection to the board . Without the
>> initialization it works fine .
>
> A few guesses:
>
> 1) Some of those EMIF data lines also serve as boot-mode and other config lines. Possibly when you configure EMIF
> you're allowing the FPGA to "override" some lines that are important to DSP health.
>
> 2) Is the FPGA connected to DSP reset? Anything that could possibly cause the FPGA to re-assert Reset would tank your
> JTAG (I assume you mean JTAG when you say "connection").
>
> 3) Are you configuring for async EMIF? And if so are you configuring to use the HRDY signal? If so maybe the FPGA
> fails to assert HRDY and EMIF permanently hangs.
>
> 4) Another outside possibility is that you configure EMIF and between FPGA and DSP sides of EMIF there is enough of a
> draw-down on your Vcc to sag the rail. That's unlikely, would only happen if you cut your switcher/regulator margins
> too close.
>
> Suggest to run your .gel file one step at a time, find the exact EMIF register write that does the damage, then report
> back. Also which C6x DSP?
>
> -Jeff

_____________________________________

Rohit,

On Thu, Apr 8, 2010 at 2:12 PM, wrote:

> Hi
> I have a custom board with a C6000 DSP and FPGA , using EMIF to connect
> both . But whenever I initialize the EMIF in the GEL , I loose connection to
> the board . Without the initialization it works fine .
>

Are you using ARDY?? If yes, then that is probably the problem. If you
start a memory cycle and ARDY does not come true, the DSP will 'hang'. If
you are in the middle of a memory cycle, the emulator cannot take control
[== lost connection].

If ARDY is not your problem, use CCS to manually initialize the EMIF [use
addresses and values from the GEL file]. After writing each word, perform an
separate operation with CCS [like viewing the registers - you can do it once
an then hit refresh after each EMIF write]. This should give you an idea
where the problem might be. Also, it will allow you to post a specific
question like -
"I am using a 6713DSK. I initialize the EMIF by writing add/data., add/data,
...
After writing d?d? to address a?a?, the system loses communication. Do you
know what might cause this??"

mikedunn

>
> Rohit
>
>

--
www.dsprelated.com/blogs-1/nf/Mike_Dunn.php

Rohit-

> I have a custom board with a C6000 DSP and FPGA , using
> EMIF to connect both . But whenever I initialize the EMIF
> in the GEL , I loose connection to the board . Without the
> initialization it works fine .

A few guesses:

1) Some of those EMIF data lines also serve as boot-mode and other config lines. Possibly when you configure EMIF
you're allowing the FPGA to "override" some lines that are important to DSP health.

2) Is the FPGA connected to DSP reset? Anything that could possibly cause the FPGA to re-assert Reset would tank your
JTAG (I assume you mean JTAG when you say "connection").

3) Are you configuring for async EMIF? And if so are you configuring to use the HRDY signal? If so maybe the FPGA
fails to assert HRDY and EMIF permanently hangs.

4) Another outside possibility is that you configure EMIF and between FPGA and DSP sides of EMIF there is enough of a
draw-down on your Vcc to sag the rail. That's unlikely, would only happen if you cut your switcher/regulator margins
too close.

Suggest to run your .gel file one step at a time, find the exact EMIF register write that does the damage, then report
back. Also which C6x DSP?

-Jeff

_____________________________________