Muhammad-

How did it go with this? The TI e2e forum reply, while maybe not giving a specific solution, overall is helpful.

I'm not sure I have any other suggestions... but if you still have the problem and can define some very specific
symptoms, I might be able to give some comments.

-Jeff

> Thank you Mr. Jeff for the reply,
> Yes u r right, the drive of DM642 is high, fast slew rates of almost 350 ps for low to high transition in case of even
> two CMOS loads.
>
> Yes I did use the termination, I used series termination at source end of 33 Ohms, using less than it produces more
> under and overshoot and using higher than that expands and elongates the rise time, so it was best to use that value
> of series termination.
>
> I routed the signals using 75 Ohm control impedance tracks, since lesser Z0 results in slower speed of the signal,
> plus I routed them on top and bottom layers of the PCB, where effective dielectric constant is less, resulting more
> propagation speed, and better setup and hold time margins.
>
> yes I did use a CPLD XC2C256 Cool Runner II, and its IBIS model, however EMIF's CE0#
> is only dedicated for SDRAM, so while accessing SDRAM (on CE0#), the address decoding part in CPLD remain silent,
> inputs High-Z, behaving like an open circuit, instead of capacitive loads, thats why I didnt mention about it.
>
> I did email it to TI, and their reply was this ...
>
> - So far we did not get feedback about potential problem on the DM642 EMIF to SDRAM. We unfiortunately can not provide
> support regarding IBIS simulation.
> You might have to make some sanity checks to have a good level of confidence on the 2 IBIS models that you are using.
> - The following might help:
> a) The C641x EMIF to SDRAM reference design application note is an example of a 150Mhz interface:
> http://focus.ti.com/docs/toolsw/folders/print/sprc137.html
> The I/O drivers of C641x and DM642 are likely to be different but it is still a good source of information for PCB
> layout example.
> b) The DM642 EVM from Spectrum digital features as well SDRAM. Again it is a good source of information for PCB layout
> example:
> http://c6000.spectrumdigital.com/evmdm642/
> c) Regarding the "Using IBIS Models for Timing Analysis - SPRA839" document:
> The way the measurement shoud be done is a bit misleading.
> Refering to section 3.1 the reference point C0 timing should not be measure at the location pointed by C. Since the
> ouput buffer impedance is very likely far from being 50 ohms you will see a lot of ringing at point C.
> Refering to the enclosed .jpg picture for example for a C6416 device the timing measurement should be done at point 2
> instead of point 3. SPRA839A does not explicitely ask to measure at point 3 but it makes it unclear that measurement
> should be done at point 2.
> Starting from time t = 0, you should simulate the tester and measure the time point 2 reaches its threshold. 2ns
> should then be subtracted from this measurement to remove the tester transmission line delay (if you added a 2ns delay
> line).
> Best regards,
>
> Anthony Berthet
> Application Support Engineer
> Texas Instruments
> European Customer Support Center
>
> ------
>
> Anyway if u have any point to share about it, I will be very happy, thanks again.
> Regards, Bilal
>
>
> --- On Thu, 6/24/10, Jeff Brower wrote:
> From: Jeff Brower
> Subject: Re: [c6x] TMS320DM642 EMIF with MT48LC4M32B@ SDRAM related ibis simulation
> To: i...@yahoo.com
> Cc: c...
> Date: Thursday, June 24, 2010, 8:09 AM
> ITS-
>
>> Hi, I have a question about TMS320DM642 EMIF related ibis simulation.
>> Previously I designed a DSP board with TMS320C6713 and all of its
>> simulations with SDRAM went perfectly ok.
>>
>> However when I performed the ibis simulation for a newer board, using
>> TMS320DM642 EMIF with Micron Technology MT48LC4M32B2 SDRAM, I get some
>> non-monotonic rise and fall waveform over the data pins (AED00 for
>> example), similar to double clocking or dual edge, and it laps for
>> about 450 ps.
>>
>> However the same simulation on Address and Clock Signals on DM642 is
>> all fine.
>>
>> The same simulation with C6713 was all ok, no non-monitonic behaviour.
>>
>> I wanted to ask is it all fine with the DM642-SDRAM interface ? , since
>> I used a very simple transmission line model of 75 Ohms for it, using
>> hyper lynx and the ti, and micron technnology provided ibis models.
>
> You mention C6713 simulation was "same" and results were Ok, so I assume that means
> the only thing that changed between DM642 and C6713 simulations was TI's IBIS model
> for EMIF.
>
> If that's the case, then possibly DM642 EMIF data bus has more drive; did you try
> series R termination? Maybe 25 ohm placed near the DM642?
>
> Also, in your simulation, you have only SDRAM connected to EMIF? No Flash, FPGA, or
> other peripheral?
>
> -Jeff

_____________________________________

Thank you Mr. Jeff for the reply,
Yes u r right, the drive of DM642 is high, fast slew rates of almost 350 ps for low to high transition in case of even two CMOS loads.

Yes I did use the termination, I used series termination at source end of 33 Ohms, using less than it produces more under and overshoot and using higher than that expands and elongates the rise time, so it was best to use that value of series termination.

I routed the signals using 75 Ohm control impedance tracks, since lesser Z0 results in slower speed of the signal, plus I routed them on top and bottom layers of the PCB, where effective dielectric constant is less, resulting more propagation speed, and better setup and hold time margins.

yes I did use a CPLD XC2C256 Cool Runner II, and its IBIS model, however EMIF's CE0#
is only dedicated for SDRAM, so while accessing SDRAM (on CE0#), the address decoding part in CPLD remain silent, inputs High-Z, behaving like an open circuit, instead of capacitive loads, thats why I didnt mention about it.

I did email it to TI, and their reply was this ...

- So far we did not get feedback about potential problem on the DM642 EMIF to SDRAM. We unfiortunately can not provide support regarding IBIS simulation.
You might have to make some sanity checks to have a good level of confidence on the 2 IBIS models that you are using.
- The following might help:
a) The C641x EMIF to SDRAM reference design application note is an example of a 150Mhz interface:
http://focus.ti.com/docs/toolsw/folders/print/sprc137.html
The I/O drivers of C641x and DM642 are likely to be different but it is still a good source of information for PCB layout example.
b) The DM642 EVM from Spectrum digital features as well SDRAM. Again it is a good source of information for PCB layout example:
http://c6000.spectrumdigital.com/evmdm642/
c) Regarding the "Using IBIS Models for Timing Analysis - SPRA839" document:
The way the measurement shoud be done is a bit misleading.
Refering to section 3.1 the reference point C0 timing should not be measure at the location pointed by C. Since the ouput buffer impedance is very likely far from being 50 ohms you will see a lot of ringing at point C.
Refering to the enclosed .jpg picture for example for a C6416 device the timing measurement should be done at point 2 instead of point 3. SPRA839A does not explicitely ask to measure at point 3 but it makes it unclear that measurement should be done at point 2.
Starting from time t = 0, you should simulate the tester and measure the time point 2 reaches its threshold. 2ns should then be subtracted from this measurement to remove the tester transmission line delay (if you added a 2ns delay line).
Best regards,

Anthony Berthet
Application Support Engineer
Texas Instruments
European Customer Support Center

------

Anyway if u have any point to share about it, I will be very happy, thanks again.
Regards, Bilal

--- On Thu, 6/24/10, Jeff Brower wrote:
From: Jeff Brower
Subject: Re: [c6x] TMS320DM642 EMIF with MT48LC4M32B@ SDRAM related ibis simulation
To: i...@yahoo.com
Cc: c...
Date: Thursday, June 24, 2010, 8:09 AM
ITS-

> Hi, I have a question about TMS320DM642 EMIF related ibis simulation.
> Previously I designed a DSP board with TMS320C6713 and all of its
> simulations with SDRAM went perfectly ok.
>
> However when I performed the ibis simulation for a newer board, using
> TMS320DM642 EMIF with Micron Technology MT48LC4M32B2 SDRAM, I get some
> non-monotonic rise and fall waveform over the data pins (AED00 for
> example), similar to double clocking or dual edge, and it laps for
> about 450 ps.
>
> However the same simulation on Address and Clock Signals on DM642 is
> all fine.
>
> The same simulation with C6713 was all ok, no non-monitonic behaviour.
>
> I wanted to ask is it all fine with the DM642-SDRAM interface ? , since
> I used a very simple transmission line model of 75 Ohms for it, using
> hyper lynx and the ti, and micron technnology provided ibis models.

You mention C6713 simulation was "same" and results were Ok, so I assume that means
the only thing that changed between DM642 and C6713 simulations was TI's IBIS model
for EMIF.

If that's the case, then possibly DM642 EMIF data bus has more drive; did you try
series R termination? Maybe 25 ohm placed near the DM642?

Also, in your simulation, you have only SDRAM connected to EMIF? No Flash, FPGA, or
other peripheral?

-Jeff

ITS-

> Hi, I have a question about TMS320DM642 EMIF related ibis simulation.
> Previously I designed a DSP board with TMS320C6713 and all of its
> simulations with SDRAM went perfectly ok.
>
> However when I performed the ibis simulation for a newer board, using
> TMS320DM642 EMIF with Micron Technology MT48LC4M32B2 SDRAM, I get some
> non-monotonic rise and fall waveform over the data pins (AED00 for
> example), similar to double clocking or dual edge, and it laps for
> about 450 ps.
>
> However the same simulation on Address and Clock Signals on DM642 is
> all fine.
>
> The same simulation with C6713 was all ok, no non-monitonic behaviour.
>
> I wanted to ask is it all fine with the DM642-SDRAM interface ? , since
> I used a very simple transmission line model of 75 Ohms for it, using
> hyper lynx and the ti, and micron technnology provided ibis models.

You mention C6713 simulation was "same" and results were Ok, so I assume that means
the only thing that changed between DM642 and C6713 simulations was TI's IBIS model
for EMIF.

If that's the case, then possibly DM642 EMIF data bus has more drive; did you try
series R termination? Maybe 25 ohm placed near the DM642?

Also, in your simulation, you have only SDRAM connected to EMIF? No Flash, FPGA, or
other peripheral?

-Jeff

_____________________________________