You mention something about estimating F'(~Oc) and then F'/4
will be my estimated carrier. My problem is how to implement this F'/4
Thanks.
--- In , Priyank Saxena <spriyank@y...> wrote: > Hi,
>
> You dont divide the carrier by 4 and then estimate it. Instead you estimate the > new carrier (which is 4 times the original
carrier) and then divide the > estimate by 4.
> For e.g.:
> If your original carrier was Fc, after the frequency multiplier it will be > 4*Fc. You estimate F' (~= 4*Fc) from this
signal and F'/4 will be your estimate > for Fc.
>
> -priyank
>
> --- "sasilion <gundamzerowing9@y...>"
<gundamzerowing9@y...> wrote:
> > Hi Guys,
> >
> > My question has something to do with frequency multiplier and
> > divider in a PLL. For example, before a QPSK is fed into a PLL, i
> > have to pass the signal through a 4th power device and bandpass it. > > I could do this by muliplying 4 times.
However, i am not sure how to > > divide the estimated carrier coming out from
the PLL by 4 times.
> >
> > Does anyone knows how to implement this frequency divider?
> >
> > Thanks.
> >
> >
>
> __________________________________________________
>
Reply by Priyank Saxena●January 21, 20032003-01-21
Hi,
You dont divide the carrier by 4 and then estimate it. Instead you estimate
the
new carrier (which is 4 times the original carrier) and then divide the
estimate by 4.
For e.g.:
If your original carrier was Fc, after the frequency multiplier it will be
4*Fc. You estimate F' (~= 4*Fc) from this signal and F'/4 will be your
estimate
for Fc.
-priyank
--- "sasilion <>" <> wrote: > Hi Guys,
>
> My question has something to do with frequency multiplier and
> divider in a PLL. For example, before a QPSK is fed into a PLL, i
> have to pass the signal through a 4th power device and bandpass it.
> I could do this by muliplying 4 times. However, i am not sure how to
> divide the estimated carrier coming out from the PLL by 4 times.
>
> Does anyone knows how to implement this frequency divider?
>
> Thanks.
>
My question has something to do with frequency multiplier and
divider in a PLL. For example, before a QPSK is fed into a PLL, i
have to pass the signal through a 4th power device and bandpass it.
I could do this by muliplying 4 times. However, i am not sure how to
divide the estimated carrier coming out from the PLL by 4 times.
Does anyone knows how to implement this frequency divider?