I trimmed down my SPI and QSPI setup code to make it easier to see and
comment on. The data received by the DSP varies unpredictably. The data
sent by the DSP looks like it has missing bits, on a scope.
Thanks in advance for any suggestions.
Rick Corey
QSPI setup snippets:
// ****** enable all QSPI chip select pins as QSPI CS, not GPIO *********
*PACNT |= 0x00804000 ; // @ $0C8F DSP0 CS pins are grounded
*PDCNT |= 0x00000030 ; // @ $0CA7 MBASE+$98
// ****** set QSPI IPL (IRQ Priority Level) in ICR4 28:31
*******************
SD_OUTWORD( (ICR4_ADDR), 0xD000 ); // P1=1 & IPL=51 does not change IPL
of INT5 INT6 SWTO & 4 reserved
*QSPI_QMR = 0xE7FF ; // DON'T SET SPE YET! // 9-bit data length, baud
divider=max, Master
// E4FF => CPOL/CPHA=0,0 DOHIE=1
// A7FF => CPOL/CPHA=1,1 DOHIE=0
*QSPI_QDLYR = 0x7FFF ; // DISable, ignore clock delay,
DelayAfterTransfer==A (try 2-C)
*QSPI_QIR = 0x1100 ; // enable only SPIFE (QSPI Tx & Rx) and ABRTL (Abort
LOCKOUT)
*QSPI_QAR = FIRST_CMD_RAM_DATA_QAR ; // select first cmd RAM entry of Q16
// write 16 words of cmd RAM and
leave these in place
for (jLoop=0; jLoop<; jLoop++) // for all future transfers
*QSPI_QDR = 0xF000; // E000, 7000 // 0xEF00 ; // make all CS
(Chip Selects) 1 with $EF00 instead of $E000
// *QSPI_QWR = 0x0F00 ; // CSIV=0 (CS return
to 0). active hi no wrap-around.
// use all queue entries, 0..15
*QSPI_QWR = 0x1F00 ; // CSIV=1 (CS return to 1). ACTIVE LOW no
wrap-around. use all queue entries, 0..15
return( 0 );
DSP setup:
// ********* setup 4 GPIO_E pins to be used by SPI: MOSI, MISO, SCLK &
/SS
E4, E5, E6 & E7
periphBitSet( 0x00F0, (unsigned short *)(GPIO_E_PER) ); // 4 GPIO pins:
peripheral enable
// John
suggests: set DDR also
// ********* SPI Data Size Register ************************************
*(unsigned short *)(SPDSR) = 0x0008 ; // SPI Data Size TRegister $8 means
word size of 9 bits
// ********* SPI Status and Control Register Section 13.9.1 DSP80x User
Manual
*(unsigned short *)(SPSCR) = 0x00ED ; // FD=Master E1=SLAVE _5MHz,
CPOL=0/CPHA=*0*/SPE disable/SPTIE&SPRIE enable
// ********* now write "SPI_DSP0_READY" to TxDataRegister to tell CF
that
DSP0 "woke up"
*(unsigned short *)(SPDTR) = SPI_DSP0_READY ;
// ********* ENable SPI: SCR |= $0002 ***********************************
periphBitSet( SPI_ENABLE_BIT_SPE, (unsigned short *)(SPSCR) ); // enable SPI
peripheral
DSP ISR using SDK IRQ dispatcher:
UWord16 WordToSendToCF= 0x0155;
*(unsigned short *)(SPDTR) = WordToSendToCF;
QSPI ISR: (I used to NOT re-save CMD RAM and QWR every time, only when I
first set up the QSPI)
CLEAR_QSPI_IRQ_SPIF ; // clear IRQ flag. writes $1101 to QIR, preserving
ABRTL & SPIFE and clearing SPIFE
// ********************************************************************
// ******** Read all 16 received words from QSPI Receive RAM ********
// ********************************************************************
*QSPI_QAR = FIRST_RX_RAM_DATA_QAR ; // select first Rx RAM entry (QSPI RAM
pointer)
for (jLoop=0; jLoop<; jLoop++)
{
RcvdWord = *QSPI_QDR ; // the QSPI RAM pointer auto-increments
etc etc
}
// ********************************************************************
// *************** Write 16 words to QSPI Transmit RAM **************
// ********************************************************************
*QSPI_QAR = FIRST_TX_RAM_DATA_QAR ; // select first Tx RAM entry (QSPI RAM
pointer)
. . .
// jloop = 0, 1 or 2 and load word if needed
for ( ; jLoop<; jLoop++) // stop sending real data
{
*QSPI_QDR = WordToSend++; // 9-bit data
if (WordToSend >= 0x01FF)
WordToSend = 0x0020;
}
ENABLE_QSPI_SPE;
return;
Reply by Corey, Rick●July 15, 20032003-07-15
Hi
I trimmed down my SPI and QSPI setup code to make it easier to see and
comment on. The data received by the DSP varies unpredictably. The data
sent by the DSP looks like it has missing bits, on a scope.
Thanks in advance for any suggestions.
Rick Corey
QSPI setup snippets:
// ****** enable all QSPI chip select pins as QSPI CS, not GPIO *********
*PACNT |= 0x00804000 ; // @ $0C8F DSP0 CS pins are grounded
*PDCNT |= 0x00000030 ; // @ $0CA7 MBASE+$98
// ****** set QSPI IPL (IRQ Priority Level) in ICR4 28:31
*******************
SD_OUTWORD( (ICR4_ADDR), 0xD000 ); // P1=1 & IPL=51 does not change IPL
of INT5 INT6 SWTO & 4 reserved
*QSPI_QMR = 0xE7FF ; // DON'T SET SPE YET! // 9-bit data length, baud
divider=max, Master
// E4FF => CPOL/CPHA=0,0 DOHIE=1
// A7FF => CPOL/CPHA=1,1 DOHIE=0
*QSPI_QDLYR = 0x7FFF ; // DISable, ignore clock delay,
DelayAfterTransfer==A (try 2-C)
*QSPI_QIR = 0x1100 ; // enable only SPIFE (QSPI Tx & Rx) and ABRTL (Abort
LOCKOUT)
*QSPI_QAR = FIRST_CMD_RAM_DATA_QAR ; // select first cmd RAM entry of Q16
// write 16 words of cmd RAM and
leave these in place
for (jLoop=0; jLoop<; jLoop++) // for all future transfers
*QSPI_QDR = 0xF000; // E000, 7000 // 0xEF00 ; // make all CS
(Chip Selects) 1 with $EF00 instead of $E000
// *QSPI_QWR = 0x0F00 ; // CSIV=0 (CS return
to 0). active hi no wrap-around.
// use all queue entries, 0..15
*QSPI_QWR = 0x1F00 ; // CSIV=1 (CS return to 1). ACTIVE LOW no
wrap-around. use all queue entries, 0..15
return( 0 );
DSP setup:
// ********* setup 4 GPIO_E pins to be used by SPI: MOSI, MISO, SCLK &
/SS
E4, E5, E6 & E7
periphBitSet( 0x00F0, (unsigned short *)(GPIO_E_PER) ); // 4 GPIO pins:
peripheral enable
// John
suggests: set DDR also
// ********* SPI Data Size Register ************************************
*(unsigned short *)(SPDSR) = 0x0008 ; // SPI Data Size TRegister $8 means
word size of 9 bits
// ********* SPI Status and Control Register Section 13.9.1 DSP80x User
Manual
*(unsigned short *)(SPSCR) = 0x00ED ; // FD=Master E1=SLAVE _5MHz,
CPOL=0/CPHA=*0*/SPE disable/SPTIE&SPRIE enable
// ********* now write "SPI_DSP0_READY" to TxDataRegister to tell CF
that
DSP0 "woke up"
*(unsigned short *)(SPDTR) = SPI_DSP0_READY ;
// ********* ENable SPI: SCR |= $0002 ***********************************
periphBitSet( SPI_ENABLE_BIT_SPE, (unsigned short *)(SPSCR) ); // enable SPI
peripheral
DSP ISR using SDK IRQ dispatcher:
UWord16 WordToSendToCF= 0x0155;
*(unsigned short *)(SPDTR) = WordToSendToCF;
QSPI ISR: (I used to NOT re-save CMD RAM and QWR every time, only when I
first set up the QSPI)
CLEAR_QSPI_IRQ_SPIF ; // clear IRQ flag. writes $1101 to QIR, preserving
ABRTL & SPIFE and clearing SPIFE
// ********************************************************************
// ******** Read all 16 received words from QSPI Receive RAM ********
// ********************************************************************
*QSPI_QAR = FIRST_RX_RAM_DATA_QAR ; // select first Rx RAM entry (QSPI RAM
pointer)
for (jLoop=0; jLoop<; jLoop++)
{
RcvdWord = *QSPI_QDR ; // the QSPI RAM pointer auto-increments
etc etc
}
// ********************************************************************
// *************** Write 16 words to QSPI Transmit RAM **************
// ********************************************************************
*QSPI_QAR = FIRST_TX_RAM_DATA_QAR ; // select first Tx RAM entry (QSPI RAM
pointer)
. . .
// jloop = 0, 1 or 2 and load word if needed
for ( ; jLoop<; jLoop++) // stop sending real data
{
*QSPI_QDR = WordToSend++; // 9-bit data
if (WordToSend >= 0x01FF)
WordToSend = 0x0020;
}
ENABLE_QSPI_SPE;
return;
Reply by Corey, Rick●July 14, 20032003-07-14
Hi
Has anyone successfully connected a ColdFire QSPI to a DSP SPI peripheral?
Could you just let me know that it really is possible?
Did you need any invertors in the circuit, or anything beyond some fancy
pull-up pull-downs for CS0 on the ColdFire side?
Has anyone successfully sent 9-bit data to a DSP SPI peripheral? I send it
1,2,3,4,5, and receive 0x022, 0x042, 0x062 etc - and many other weird bit
patterns. As if many SCLKs were being missed, but in some rigid pattern.
I'm concentrating on CPHA=1 so that ~SS will be ignored.
I've posted to Digital DNA, and they just handed the request from one
person
to another for a full week now.
Of course, testing with a Motorola evaluation board just confirms that the
DSP chips they put into our five eval boards were all full of SPI errata,
since none are Rev. F or even Rev. E.
Any clues at all would be greatly appreciated.
Rick Corey
Senior Software Engineer
DPC Instrument Systems Division
Reply by Corey, Rick●July 14, 20032003-07-14
Hi
Has anyone successfully connected a ColdFire QSPI to a DSP SPI peripheral?
Could you just let me know that it really is possible?
Did you need any invertors in the circuit, or anything beyond some fancy
pull-up pull-downs for CS0 on the ColdFire side?
Has anyone successfully sent 9-bit data to a DSP SPI peripheral? I send it
1,2,3,4,5, and receive 0x022, 0x042, 0x062 etc - and many other weird bit
patterns. As if many SCLKs were being missed, but in some rigid pattern.
I'm concentrating on CPHA=1 so that ~SS will be ignored.
I've posted to Digital DNA, and they just handed the request from one
person
to another for a full week now.
Of course, testing with a Motorola evaluation board just confirms that the
DSP chips they put into our five eval boards were all full of SPI errata,
since none are Rev. F or even Rev. E.
Any clues at all would be greatly appreciated.
Rick Corey
Senior Software Engineer
DPC Instrument Systems Division
Reply by Corey, Rick●July 7, 20032003-07-07
Hi
I am trying to connect a 5272 ColdFire QSPI peripheral to a DSP 56803 SPI
peripheral. I can get the 5272 ColdFire QSPI to loopback to itself fine. I
can get the 56803 DSP SPI to loop back to itself fine. ISRs fire, data
clocks back and forth, and it looks pretty clean on a scope. I have not yet
tried one DSP to another DSP, or one ColdFire to another (I expect those to
be painless except for coming up with tiny cable connectors.
It is just that the data I read is wrong. The best data I've seen has
been
mostly << left-shifted by one bit << when read by the DSP from
the
ColdFire.
I've attached my DSP and 5272 code, cut down to just the relevant lines.
I
have also tried *many* other variations on register values SPSCR, QMR, Cmd
RAM and QWR. I am currently testing with a Motorola DSP eval board
(DSP56F803EVM) and a Netburner 5272 eval board (CFV2-66). The DSP date code
is ZKAC0115.
Do you think QSPI-to-SPI requires inverters on some signal lines?
Should I try more seemingly wrong combinations of polarities and CPHA?
Has anyone here succeed in connecting a QSPI to a SPI?
Could you suggest problems that I might be unaware of, such as errata in the
SPI or QSPI documentation?
Are there any more details I can supply to clarify what I might be doing
wrong?
I've read that the 5272 QSPI is similar to the QSM in a MC68332. I'm
using
9-bit data. After the first few tests, I went to the lowest baud rate and
longest delays I could choose. The 5272 has to be the Master, and the DSP
is the Slave.
Thanks in advance for any suggestions.
<<SPI-QSPI Question .doc>>
Rick Corey
Senior Software Engineer
DPC Instrument Systems Division