Hi 

I'm using a 6713(slave) with a Atmel AT91RM9200 (Master), and I have had
the same problem, as a possible solution I have tried to use the multiple
numbers of elements in a frame. 

The data transfered between the Atmel and the dsp seems to get corrupted
in the DSP. I.E if I send 8 words or 16 bits in a block, when I receive
them in the DSP I will see 8 words but only a few of them will be the
words I expected! 
The Atmel seems extends the clk on the last clk of every element, where a
chip select cycle should be, am I missing some key combination of settings
here or is it the extended clk thats messing things up?


Regards
DaveE


>On 2 Jan 2004 10:57:51 -0800, a_z129@yahoo.com (Zia) wrote:
>
>>Hi All:
>>
>>I am trying to communicate between C5502 and an Atmel processor with
>>ARM7 core. We want to do the communication using SPI protocol with ARM
>>acting as SPI master and C5502 acting as Slave.
>>
>>In our design, the ARM asserts the slave-enable(SS) signal only once
>>at the start of transmission of the frame and it stays active
>>throughout the transmission of all words in a single frame. The
>>transmission of each word is thus facilitated by activating and
>>deactivating the shift-clock(SCLK) by the ARM. This mode of operation
>>is necessary for smooth DMA operation of the ARM.
>>Now, while testing, it appears that DSP does'nt work properly as Slave
>>if slave-enable signal is not asserted and deasserted for transfer of
>>every single word in the frame but it does work fine otherwise.
>>
>>My question is: does anyone have any idea if our desired mode of
>>operation could actually work? and if it can, what needs to be done in
>>the McBSP configuration?
>> 
>>The DSP manual(spru592.pdf) is ambiguous about it. 
>
>I guess you mean that:
>
>"The McBSP requires an active edge of the slave-enable signal on the
>FSX input for each transfer. This means that the master device must
>assert the slave-enable signal at the beginning of each transfer, and
>deassert the signal after the completion of each packet transfer; the
>slave-enable signal cannot remain active between transfers."
>
>So what this means all depends on the definition of "packet transfer".
>A packet is defined by X/RWDLENx and X/RFRLENx, the latter being
>related to the FSRX signal. Unfortunately from your point of view, if
>you want to use SPI (Clock-Stop) mode on the C5502, you have to set
>X/RFRLENx to 0 to give a frame length of 1 serial word (see section
>6.3, table 6-1 of spru592a).
>
>So basically what you want to do can't be done without some external
>logic.
>
>
>Best Regards
>John McCabe
>
>To reply by email replace 'nospam' with 'assen'
>




		
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On 2 Jan 2004 10:57:51 -0800, a_z129@yahoo.com (Zia) wrote:

>Hi All:
>
>I am trying to communicate between C5502 and an Atmel processor with
>ARM7 core. We want to do the communication using SPI protocol with ARM
>acting as SPI master and C5502 acting as Slave.
>
>In our design, the ARM asserts the slave-enable(SS) signal only once
>at the start of transmission of the frame and it stays active
>throughout the transmission of all words in a single frame. The
>transmission of each word is thus facilitated by activating and
>deactivating the shift-clock(SCLK) by the ARM. This mode of operation
>is necessary for smooth DMA operation of the ARM.
>Now, while testing, it appears that DSP does'nt work properly as Slave
>if slave-enable signal is not asserted and deasserted for transfer of
>every single word in the frame but it does work fine otherwise.
>
>My question is: does anyone have any idea if our desired mode of
>operation could actually work? and if it can, what needs to be done in
>the McBSP configuration?
> 
>The DSP manual(spru592.pdf) is ambiguous about it. 

I guess you mean that:

"The McBSP requires an active edge of the slave-enable signal on the
FSX input for each transfer. This means that the master device must
assert the slave-enable signal at the beginning of each transfer, and
deassert the signal after the completion of each packet transfer; the
slave-enable signal cannot remain active between transfers."

So what this means all depends on the definition of "packet transfer".
A packet is defined by X/RWDLENx and X/RFRLENx, the latter being
related to the FSRX signal. Unfortunately from your point of view, if
you want to use SPI (Clock-Stop) mode on the C5502, you have to set
X/RFRLENx to 0 to give a frame length of 1 serial word (see section
6.3, table 6-1 of spru592a).

So basically what you want to do can't be done without some external
logic.


Best Regards
John McCabe

To reply by email replace 'nospam' with 'assen'

Hi All:

I am trying to communicate between C5502 and an Atmel processor with
ARM7 core. We want to do the communication using SPI protocol with ARM
acting as SPI master and C5502 acting as Slave.

In our design, the ARM asserts the slave-enable(SS) signal only once
at the start of transmission of the frame and it stays active
throughout the transmission of all words in a single frame. The
transmission of each word is thus facilitated by activating and
deactivating the shift-clock(SCLK) by the ARM. This mode of operation
is necessary for smooth DMA operation of the ARM.
Now, while testing, it appears that DSP does'nt work properly as Slave
if slave-enable signal is not asserted and deasserted for transfer of
every single word in the frame but it does work fine otherwise.

My question is: does anyone have any idea if our desired mode of
operation could actually work? and if it can, what needs to be done in
the McBSP configuration?
 
The DSP manual(spru592.pdf) is ambiguous about it. I have also checked
McBSP operation in spru302(C54) and spru190(C6x) but none helped. Any
help/comment will be appreciated.


Thanks,
Zia