praveen wrote:

> Hello,
> I am designed a DSP based which measures the rotation rate (sagnac
> phase). But the problem i am facing is that jitter in the clock which
> is used as sampling input to the ADC will spoil by algorithm. The
> sampling point is very crucial.
> How can i solved this problem.
> 
> suggest we a solution
> waiting for reply
> with regards
> praveen

Your question is too diffuse. You have written, in effect, "What I'm
doing isn't good enough. How can I get better results without
necessarily doing it better?

How much jitter do you experience? How much jitter can you afford? What
to you mean by "Sagnac phase"? Surely, you measure the interference
pattern -- one of average, not instantaneous, intensity. If you in fact
measure the individual phases of counter-rotating light beams, I very
much want to know how you do that, and so would most others here.

Jerry
-- 
Engineering is the art of making what you want from things you can get.
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"praveen" <praveenkumar1979@rediffmail.com> wrote in message
news:ff8a3afb.0311280552.57df7d1d@posting.google.com...
> Hello,
> I am designed a DSP based which measures the rotation rate (sagnac
> phase). But the problem i am facing is that jitter in the clock which
> is used as sampling input to the ADC will spoil by algorithm. The
> sampling point is very crucial.
> How can i solved this problem.

First you need to quantify the problem. How much jitter can you afford?
There are no zero jitter clocks. Some have less jitter and some more...

/Mikhail

Hello,
I am designed a DSP based which measures the rotation rate (sagnac
phase). But the problem i am facing is that jitter in the clock which
is used as sampling input to the ADC will spoil by algorithm. The
sampling point is very crucial.
How can i solved this problem.

suggest we a solution
waiting for reply
with regards
praveen