Reply by DruidNei June 2, 20122012-06-02
This might be the issue, I will check it out. 
Big thanks for your help.
Reply by dvsarwate June 1, 20122012-06-01
On Jun 1, 9:35&#4294967295;am, "DruidNei" <DruidNei@n_o_s_p_a_m.gmail.com> wrote:
> I'm currently developing DVB-T transmitter on FPGA platform. DVB-T standard > (ETSI EN 300 744 v1.6.1) says that in 16-QAM, non-hierarchical transmission > mode, bit interleaver uses following interleavers: > I0: H0(w) = w > I1: H1(w) = (w + 63) mod 126 > I2: H2(w) = (w + 105) mod 126 > I3: H3(w) = (w + 42) mod 126 > > I've tested it both using a reference model (found here:http://dante.diei.unipg.it/~baruffa/dvbt/index.php) and in hardware FPGA > device, and came to a conclusion that in fact 16-QAM mode uses interleavers > I0, I1, I4 and I5, despite what is written in the standard. > > I4: H4(w) = (w + 21) mod 126 > I5: H5(w) = (w + 84) mod 126 > > I've managed to successfully receive and decode such signal using > commercial (R&S) TV signals analyser. It didn't work when using I2 and I3. > > I want to do 64-QAM mode next and I would like to know what is the right > order of interleavers without reverse engineering it from reference model > by trial and error. I would also like to base my work on dvb-t standard > documents. > > My question is: am I reading the standard wrong? why is there such a > difference?
There may be an issue of interpretation here. Note that 21 + 105 = 126 and 42 + 84 = 126. So, if x = w + 21 mod 126, then w = x - 21 mod 126 = x + 105 mod 126, and so on. With x = w + 63 mod 126, w = x - 63 mod 126 = x + 63 mod 126. Dilip Sarwate
Reply by DruidNei June 1, 20122012-06-01
I'm currently developing DVB-T transmitter on FPGA platform. DVB-T standard
(ETSI EN 300 744 v1.6.1) says that in 16-QAM, non-hierarchical transmission
mode, bit interleaver uses following interleavers:
I0: H0(w) = w
I1: H1(w) = (w + 63) mod 126
I2: H2(w) = (w + 105) mod 126
I3: H3(w) = (w + 42) mod 126

I've tested it both using a reference model (found here:
http://dante.diei.unipg.it/~baruffa/dvbt/index.php) and in hardware FPGA
device, and came to a conclusion that in fact 16-QAM mode uses interleavers
I0, I1, I4 and I5, despite what is written in the standard. 

I4: H4(w) = (w + 21) mod 126
I5: H5(w) = (w + 84) mod 126

I've managed to successfully receive and decode such signal using
commercial (R&S) TV signals analyser. It didn't work when using I2 and I3.

I want to do 64-QAM mode next and I would like to know what is the right
order of interleavers without reverse engineering it from reference model
by trial and error. I would also like to base my work on dvb-t standard
documents.

My question is: am I reading the standard wrong? why is there such a
difference?