mjames2393@gmail.com wrote in
news:a2792858-0144-4b9f-8139-13e506528e06@googlegroups.com:
> There is no way around the number of filter taps.
>
> I'm looking for a DSP development board. Is there anything out there on
> the market which can do the job? I don't want to mess around with FPGAs
> and other types of solutions. A TigerSHARC board maybe?
>
You could do this computation with a SHARC DSP. We have done much larger
FIRs at 192k sampling and 8 channels using a ADSP-21469 with DDR2 SDRAM.
However, you are not going to do it with time domain convolution in a SHARC
or similar device.
Assume 450M clock and 96k sampling. This means you have 450M/96k = 4687
instructions per sample available. You could double this number assuming
SIMD.
A simple convolution FIR takes about 1 instruction per tap (non SIMD) plus
a little overhead. This means you could do approximately 1.5 filters
calculations or 3 in SIMD. You also have a little overhead to account for
which reduces this number a little bit.
A workable solution is frequency domain convolution. This method is more
difficult to write but very efficient. Do a Google search on partioned
convolution for descriptions.
If you only need a single solution, an ADI 21469 EZ KIT would be the most
economical. If you need to incorporate this into a real product, our
dspblok 21469 module might be a good choice.
Al Clark
www.danvillesignal.com
Reply by ●June 26, 20122012-06-26
There is no way around the number of filter taps.
I'm looking for a DSP development board. Is there anything out there on the market
which can do the job? I don't want to mess around with FPGAs and other types of solutions. A TigerSHARC board maybe?
Reply by Tim Wescott●June 26, 20122012-06-26
On Mon, 25 Jun 2012 20:15:49 -0700, Mauritz Jameson wrote:
> Which development board would you recommend for a real-time audio
> application which involves 8 FIR filters? Each FIR filter has 3000 taps
> and it must be able to process audio blocks at 96kHz.
>
> As far as I understand that is equivalent of approx. 2304 MMAC/sec if
> the core CPU is to perform the filtering. I'm not sure I will be able to
> find a development board that can handle this? Or am I wrong?
>
> I know that some of the SHARC processors incorporate hardware
> accelerators for stuff like the above to offload the core CPU. If the
> above is realistic for a real-time app, what kind of development board
> should I buy for prototyping my algorithm? SHARC ? TigerSHARC?
3000 taps seems like an awfully long filter -- do they _all_ need to be
that long? Is there any other way you can attain your goals that doesn't
involve such intensive processing?
The filters wouldn't all have to run on the same processor -- right? So
you could have more than one processor running, or a DSP with an FPGA
helping.
--
Tim Wescott
Control system and signal processing consulting
www.wescottdesign.com
Reply by glen herrmannsfeldt●June 26, 20122012-06-26
Mauritz Jameson <mjames2393@gmail.com> wrote:
> Which development board would you recommend for a real-time audio
> application which involves 8 FIR filters? Each FIR filter has 3000
> taps and it must be able to process audio blocks at 96kHz.
So, 16 bits wide? Have you thought about doing it in an FPGA?
I think it can be done in a systolic array in a reasonable
sized FPGA, maybe a large Spartan-6. I think I know how to do
it at 100 taps and 100MHz. With a little work on multiplexing
it should be able to run 50,000 taps at 100kHz. (There is some
overhead, so I only claim 50,000.)
> As far as I understand that is equivalent of approx. 2304 MMAC/sec if
> the core CPU is to perform the filtering. I'm not sure I will be able
> to find a development board that can handle this? Or am I wrong?
How much should they cost, and how many do you need?
-- glen
Reply by Mauritz Jameson●June 26, 20122012-06-26
Which development board would you recommend for a real-time audio
application which involves 8 FIR filters? Each FIR filter has 3000
taps and it must be able to process audio blocks at 96kHz.
As far as I understand that is equivalent of approx. 2304 MMAC/sec if
the core CPU is to perform the filtering. I'm not sure I will be able
to find a development board that can handle this? Or am I wrong?
I know that some of the SHARC processors incorporate hardware
accelerators for stuff like the above to offload the core CPU. If the
above is realistic for a real-time app, what kind of development board
should I buy for prototyping my algorithm? SHARC ? TigerSHARC?