Dear Clark,
       Thanks for your time. Sorry for the late reply. We are planning
to change the tlv320aic27 to the ad1881 codec. currently we are unable
to change the ac97 codec, since it is an easy upgradation of our old
board. but now we are seriously thinking for the need of the ac97
codec. I afraid that i might did some wrong intialiazation or miss
some specific technique/order of intialization for the current
codec(tlv320aic27). Anyway i will tell you more when the new board
arrives.
rgds
ajith



Al Clark <dsp@danvillesignal.com> wrote in message news:<Xns943961253334Aaclarkdanvillesignal@66.133.130.30>...
> ajith_pc@yahoo.com (Ajith Kumar P C) wrote in
> news:18eae751.0311200219.4953b71d@posting.google.com: 
> 
> > Hi,
> > 
> > I am facing a problem for initializing the codec at variable sample
> > rate. I will try to explain the problem in detail. I am working on a
> > custom made board where an AC'97 rev 2.1 codec (TLV320AIC27) is
> > connected to a SHARC processor (ADSP- 21065L)'s serial port and the
> > serial port is in multi channel mode. My aim is to acquire the data at
> > 8K sample rate. The following are the pin connections:
> > 
> > Codec Reset          -     Flag Pin at ADSP
> > BIT_CLK          -     Serial CLK (for both Rx and Tx) SPORT1
> > (generated by the codec)
> > Frame_sync          -     RFS(generated by the SHARC)
> > TFS of the SPORT is left unused.  
> > 
> > The codec initialization and the data acquisition procedures are as
> > follows:
> > First disable the codec for a certain time interval by de-asserting
> > the flag pin and enables the codec by asserting the Flag pin. Wait for
> > the Codec ready (by checking the first bit of the incoming stream).
> > Then initialize the SPORT control registers.
> > 
> > After that the ADC and DAC's are powered down and powered up again as
> > specified in the power down/up state diagrams shown in the
> > tlv320aic20's data sheet. In the data sheet it is not mentioned that
> > this procedure is essential for proper aligning of ADC and DAC data.
> > This was done because in the application manual "interfacing the
> > ADSP-21065L SHARC DSP to the AD1819A AC'97 Sound Port Codec", it is
> > mentioned that for proper aligning of the incoming and outgoing data
> > as left and right pairs, we should power down and up the codec's ADC
> > and DAC. I had tried with out this power down/up module also.
> > 
> > In the first case (with power down/up module), the codec works fine
> > some times? samples the data by the ADC and DAC sends the demands for
> > the data at a single frame. But if we try continuously loading the
> > same program, some times it fails ? seems that ADC and DAC are not
> > synchronizing. ADC shows valid data in some frame, but the DAC is not
> > requesting any data for that frame. Some times DAC's left and right
> > channel data request not in the same frame (data acquire through
> > LINE_IN). Anyway the requesting interval is keeping periodicity ?
> > means any of the DAC requests for the data for certain time interval,
> > the next request comes only after 6 frames (sample rate is 8K).
> > 
> > In the second case the failure rate is more than the first case. 
> > 
> > We are going to replace this tlv320aic20 (it is obsolete now) with an
> > AD1881A codec. But I could not find a solution for the above problem.
> > Please give some directions.
> > 
> > PS: the transmission and reception are in chained DMA mode with Tx
> > interrupt enabled ? the 8 slots of 32bit word length is used for
> > communicating with AC'97 codec ? 8*32 = 256bits. Out of 8 slots only 3
> > slots ? 3*32 = 96 bits, (up to slot 4 of the AC'97 frame) - are active
> > for reception and 5 slots for transmission in order to make sure that
> > the 4th AC'97 slot data should be received when the interrupt was
> > generated.
> > 
> > rgds
> > ajith
> > 
> 
> AC'97 codecs are tricky as you have found out. On most AC'97 codecs the 
> samples will arrive at the same time if the variable sampling rate is an 
> even submultiple of 48k which is true in your case (48k/6 = 8k). As far 
> as I know, the L & R channels are always sampled at the same time and the 
> DACs are also time aligned even if there are samples in different time 
> slots. 
> 
> You may also find that AC'97 codecs will behave differently from 
> manufacturer to manufacturer. We have tested many different AC'97 codecs. 
> The ADI versions are fine. We use Wolfson WM9707 AC'97 codecs. You may 
> find that the passive parts you need around the Wolfson part will be more 
> like the TI part that the AD1881A.
> 
> I collect samples in a ring buffer as discussed in the ADI note you 
> referenced. (I am listed as the contributor of this idea in the ap note).
> 
> My best recommendation to you is to reconsider the need for an AC'97 
> codec. Unless you need the mixer functions, AC'97 codecs are not worth 
> the trouble. There are many parts designed for 96K sampling that are 
> easier to use. Wolfson, Cirrus Logic, Analog Devices, TI and AKM are all 
> good suppliers of these parts.

ajith_pc@yahoo.com (Ajith Kumar P C) wrote in
news:18eae751.0311200219.4953b71d@posting.google.com: 

> Hi,
> 
> I am facing a problem for initializing the codec at variable sample
> rate. I will try to explain the problem in detail. I am working on a
> custom made board where an AC'97 rev 2.1 codec (TLV320AIC27) is
> connected to a SHARC processor (ADSP- 21065L)'s serial port and the
> serial port is in multi channel mode. My aim is to acquire the data at
> 8K sample rate. The following are the pin connections:
> 
> Codec Reset          -     Flag Pin at ADSP
> BIT_CLK          -     Serial CLK (for both Rx and Tx) SPORT1
> (generated by the codec)
> Frame_sync          -     RFS(generated by the SHARC)
> TFS of the SPORT is left unused.  
> 
> The codec initialization and the data acquisition procedures are as
> follows:
> First disable the codec for a certain time interval by de-asserting
> the flag pin and enables the codec by asserting the Flag pin. Wait for
> the Codec ready (by checking the first bit of the incoming stream).
> Then initialize the SPORT control registers.
> 
> After that the ADC and DAC's are powered down and powered up again as
> specified in the power down/up state diagrams shown in the
> tlv320aic20's data sheet. In the data sheet it is not mentioned that
> this procedure is essential for proper aligning of ADC and DAC data.
> This was done because in the application manual "interfacing the
> ADSP-21065L SHARC DSP to the AD1819A AC'97 Sound Port Codec", it is
> mentioned that for proper aligning of the incoming and outgoing data
> as left and right pairs, we should power down and up the codec's ADC
> and DAC. I had tried with out this power down/up module also.
> 
> In the first case (with power down/up module), the codec works fine
> some times� samples the data by the ADC and DAC sends the demands for
> the data at a single frame. But if we try continuously loading the
> same program, some times it fails � seems that ADC and DAC are not
> synchronizing. ADC shows valid data in some frame, but the DAC is not
> requesting any data for that frame. Some times DAC's left and right
> channel data request not in the same frame (data acquire through
> LINE_IN). Anyway the requesting interval is keeping periodicity �
> means any of the DAC requests for the data for certain time interval,
> the next request comes only after 6 frames (sample rate is 8K).
> 
> In the second case the failure rate is more than the first case. 
> 
> We are going to replace this tlv320aic20 (it is obsolete now) with an
> AD1881A codec. But I could not find a solution for the above problem.
> Please give some directions.
> 
> PS: the transmission and reception are in chained DMA mode with Tx
> interrupt enabled � the 8 slots of 32bit word length is used for
> communicating with AC'97 codec � 8*32 = 256bits. Out of 8 slots only 3
> slots � 3*32 = 96 bits, (up to slot 4 of the AC'97 frame) - are active
> for reception and 5 slots for transmission in order to make sure that
> the 4th AC'97 slot data should be received when the interrupt was
> generated.
> 
> rgds
> ajith
> 

AC'97 codecs are tricky as you have found out. On most AC'97 codecs the 
samples will arrive at the same time if the variable sampling rate is an 
even submultiple of 48k which is true in your case (48k/6 = 8k). As far 
as I know, the L & R channels are always sampled at the same time and the 
DACs are also time aligned even if there are samples in different time 
slots. 

You may also find that AC'97 codecs will behave differently from 
manufacturer to manufacturer. We have tested many different AC'97 codecs. 
The ADI versions are fine. We use Wolfson WM9707 AC'97 codecs. You may 
find that the passive parts you need around the Wolfson part will be more 
like the TI part that the AD1881A.

I collect samples in a ring buffer as discussed in the ADI note you 
referenced. (I am listed as the contributor of this idea in the ap note).

My best recommendation to you is to reconsider the need for an AC'97 
codec. Unless you need the mixer functions, AC'97 codecs are not worth 
the trouble. There are many parts designed for 96K sampling that are 
easier to use. Wolfson, Cirrus Logic, Analog Devices, TI and AKM are all 
good suppliers of these parts. 


-- 
Al Clark
Danville Signal Processing, Inc.
--------------------------------------------------------------------
Purveyors of Fine DSP Hardware and other Cool Stuff
Available at http://www.danvillesignal.com

Hi,

I am facing a problem for initializing the codec at variable sample
rate. I will try to explain the problem in detail. I am working on a
custom made board where an AC'97 rev 2.1 codec (TLV320AIC27) is
connected to a SHARC processor (ADSP- 21065L)'s serial port and the
serial port is in multi channel mode. My aim is to acquire the data at
8K sample rate. The following are the pin connections:

Codec Reset		-	Flag Pin at ADSP
BIT_CLK		-	Serial CLK (for both Rx and Tx) SPORT1 (generated by the
codec)
Frame_sync		-	RFS(generated by the SHARC)
TFS of the SPORT is left unused.  

The codec initialization and the data acquisition procedures are as
follows:
First disable the codec for a certain time interval by de-asserting
the flag pin and enables the codec by asserting the Flag pin. Wait for
the Codec ready (by checking the first bit of the incoming stream).
Then initialize the SPORT control registers.

After that the ADC and DAC's are powered down and powered up again as
specified in the power down/up state diagrams shown in the
tlv320aic20's data sheet. In the data sheet it is not mentioned that
this procedure is essential for proper aligning of ADC and DAC data.
This was done because in the application manual "interfacing the
ADSP-21065L SHARC DSP to the AD1819A AC'97 Sound Port Codec", it is
mentioned that for proper aligning of the incoming and outgoing data
as left and right pairs, we should power down and up the codec's ADC
and DAC. I had tried with out this power down/up module also.

In the first case (with power down/up module), the codec works fine
some times� samples the data by the ADC and DAC sends the demands for
the data at a single frame. But if we try continuously loading the
same program, some times it fails � seems that ADC and DAC are not
synchronizing. ADC shows valid data in some frame, but the DAC is not
requesting any data for that frame. Some times DAC's left and right
channel data request not in the same frame (data acquire through
LINE_IN). Anyway the requesting interval is keeping periodicity �
means any of the DAC requests for the data for certain time interval,
the next request comes only after 6 frames (sample rate is 8K).

In the second case the failure rate is more than the first case. 

We are going to replace this tlv320aic20 (it is obsolete now) with an
AD1881A codec. But I could not find a solution for the above problem.
Please give some directions.

PS: the transmission and reception are in chained DMA mode with Tx
interrupt enabled � the 8 slots of 32bit word length is used for
communicating with AC'97 codec � 8*32 = 256bits. Out of 8 slots only 3
slots � 3*32 = 96 bits, (up to slot 4 of the AC'97 frame) - are active
for reception and 5 slots for transmission in order to make sure that
the 4th AC'97 slot data should be received when the interrupt was
generated.

rgds
ajith