If I remember correctly and I know only how it works in the 5501/5502:
The DMA reads data from a specified buffer in start/end of clock cycle and
then writes to a specified buffer in the end/start of the cycle. This means
that in one cycle, your read buffer has been filled by the DMA and your
write buffer has been "emptied" by the DMA. So, the read and write is not
exactly simultaneous but are clocked to either half of the clock cycle,
making it look simultaneous to you.

I hope I made sense =)

-Sima

2008/9/16 chenkaishiyi

> Hi,everyone
> the TI documents illustrate that two DMA controller can't access the same
> port simultaneously,and the port defined as DARAM SARAM EMIF peripheral.
> so if I implement a program in DARAM spaces use two DMA ——one for read
> ,anther for write,then their can't work simultaneously in one clock
> cycle.
> Could anyone who know about this tell me if my understanding is right?
> Could CPU and DMA access DARAM space simultaneously in one clock cycle?
>
> 2008-09-16
> ------------------------------
> chenkaishiyi
>
> Start a New Thread

Hi,everyone
the TI documents illustrate that two DMA controller can't access the same port simultaneously,and the port defined as DARAM SARAM EMIF peripheral.
so if I implement a program in DARAM spaces use two DMA one for read ,anther for write,then their can't work simultaneously in one clock
cycle.
Could anyone who know about this tell me if my understanding is right? Could CPU and DMA access DARAM space simultaneously in one clock cycle?

2008-09-16
chenkaishiyi Start a New Thread