Tim Wescott <tim@seemywebsite.please> wrote:
> On Wed, 16 Jan 2013 10:36:30 -0500, Randy Yates wrote:

(snip)
>> Yeah, but can you use 14 good bits of a crappy 16 bit dac into 
>> a 20 bit dac???
 
> Not really -- crappy 16-bit DACs are crappy because each code is off by 
> an amount that's crappy for a 16-bit DAC.  Choosing every 4th code will 
> give you a 14-bit DAC where each code is off by an amount that's crappy 
> for a 16-bit DAC (but possibly not a 14-bit DAC).
 
> Part of the allure of a sigma-delta DAC with a "one bit" conversion 
> element is that you can just throw all of the differential and 
> nonlinearity error problems out the window.  You still need to worry 
> about gain and other effects that might cause various errors, but at 
> least your differential and nonlinearity problems are taken care of.
 
> (And no, I don't know what all the sources of error are in a Sigma-Delta 
> DAC, although for starters you need to worry about the conversion element 
> having tightly matched settling characteristics in both the positive-
> going and negative-going directions, and you have to follow that 
> conversion element with analog circuitry that has a dynamic range all the 
> way down to your desired precision -- and even 16-bit analog circuitry 
> isn't trivial: 24 bits is obviously doable, but it ain't trivial!)

But back to my previous question, won't some of those errors be random,
or at least have a random component? If so, then they will average out
over a large number of samples, even if they don't for just one.

One that I just thought about is clock jitter, which may or may not
be random. The clock might phase-lock, or try to, to some other clock,
making a non-random fluctuation in the clock timing.

(Reminds me of a story from many years ago about the 74LS124 dual VCO.
Stories go that the two phase-lock so easily that it is not possible to
use both of them.)

http://www.alldatasheet.com/datasheet-pdf/pdf/28062/TI/74LS124.html

-- glen

On Wed, 16 Jan 2013 10:36:30 -0500, Randy Yates wrote:

> Robert Adams <robert.adams@analog.com> writes:
> 
>> The shaped noise will fold down in the presence of non linearity. You
>> can make an ideal 16 bit dac into a 20 bit dac this way, but you can't
>> make a crappy 16 bit dac into a good 20 bit dac, unless the dac errors
>> are gentle curves with no low-level dnl errors
> 
> Yeah, but can you use 14 good bits of a crappy 16 bit dac into a 20 bit
> dac???

Not really -- crappy 16-bit DACs are crappy because each code is off by 
an amount that's crappy for a 16-bit DAC.  Choosing every 4th code will 
give you a 14-bit DAC where each code is off by an amount that's crappy 
for a 16-bit DAC (but possibly not a 14-bit DAC).

Part of the allure of a sigma-delta DAC with a "one bit" conversion 
element is that you can just throw all of the differential and 
nonlinearity error problems out the window.  You still need to worry 
about gain and other effects that might cause various errors, but at 
least your differential and nonlinearity problems are taken care of.

(And no, I don't know what all the sources of error are in a Sigma-Delta 
DAC, although for starters you need to worry about the conversion element 
having tightly matched settling characteristics in both the positive-
going and negative-going directions, and you have to follow that 
conversion element with analog circuitry that has a dynamic range all the 
way down to your desired precision -- and even 16-bit analog circuitry 
isn't trivial: 24 bits is obviously doable, but it ain't trivial!)

-- 
Tim Wescott
Control system and signal processing consulting
www.wescottdesign.com

Sorry, I meant "you could get away with a 12-bit DAC that was 18-bits linear"

I'll amend that slightly. Non linearity will turn the shaped noise )good) into white noise (bad). 

 However that white noise will be spread over the total bandwidth. Since we are talking about sigma-delta, you must be over sampling by some factor, and therefore you win by the square-root of the over sampling factor.

So for a practical example, if you want to turn a 12 bit DAC into a 20 bit DAC, you need noise suppression on the order of 48 db, so I would guess you need to over sample by about 16. That means the 20-bit accuracy requirement I mentioned before could be relaxed by 2 bits, so you could get away with a 20-bit DAC that was 18-bits linear.

Of course this glosses over lots of potential idle-tone generation issues, and as a practical matter you might find you need better accuracy than this.

Bob

Only if those 14 bits are accurate to the 20-bit level

Robert Adams <robert.adams@analog.com> writes:

> The shaped noise will fold down in the presence of non linearity. You
> can make an ideal 16 bit dac into a 20 bit dac this way, but you can't
> make a crappy 16 bit dac into a good 20 bit dac, unless the dac errors
> are gentle curves with no low-level dnl errors

Yeah, but can you use 14 good bits of a crappy 16 bit dac into a 20 bit
dac???
-- 
Randy Yates
Digital Signal Labs
http://www.digitalsignallabs.com

The shaped noise will fold down in the presence of non linearity. You can make an ideal 16 bit dac into a 20 bit dac this way, but you can't make a crappy 16 bit dac into a good 20 bit dac, unless the dac errors are gentle curves with no low-level dnl errors

Bob

Tim Wescott <tim@seemywebsite.com> wrote:

(snip, I wrote)
>> Sounds like what physics calls random error vs. systematic error.
 
>> The former you can average out, the latter you can't.
 
> (balance snipped)
 
> It isn't really systematic vs. random.  Both are deterministic 
> ("systematic").  But DACs often integral error that's only a bit higher 
> than the differential error, instead of sqrt(2^bits) or something scary 
> like that.  So the percentage error going from one bit to the next may be 
> 50% (1/2 LSB is a common measure for differential error), but if the DAC 
> maker has held the integral nonlinearity error down, then that error will 
> not propagate to the next LSB and the next.  Hence, scrambling and 
> averaging may help.

OK, I think I see that. I was thinking in terms of the flash ADC, 
where it is easier to see the effect of non-linearity. For other ones,
yes, it is more complicated.
 
> Like I said, it'll take some experimentation and deep study of the data 
> sheets.

-- glen

On Tue, 15 Jan 2013 23:10:15 +0000, glen herrmannsfeldt wrote:

> Tim Wescott <tim@seemywebsite.com> wrote:
>> On Tue, 15 Jan 2013 15:22:23 -0500, Randy Yates wrote:
> 
> (snip)
>>> Could we linearize a multi-bit DAC converter that may have
>>> nonlinearity in the lower bits by quantizing to a coarser resolution
>>> and utilizing a delta sigma modulator to improve the SNR?
> 
> (snip)
>>> Or do DAC nonlinearities not operate this way?
>  
>> Some do, some don't.
>  
>> I think your best bet for understanding this would be to go look at
>> some DAC data sheets, or maybe find an app note that discusses the
>> difference between "differential nonlinearity" and "integral
>> nonlinearity".
> 
> Sounds like what physics calls random error vs. systematic error.
> 
> The former you can average out, the latter you can't.

(balance snipped)

It isn't really systematic vs. random.  Both are deterministic 
("systematic").  But DACs often integral error that's only a bit higher 
than the differential error, instead of sqrt(2^bits) or something scary 
like that.  So the percentage error going from one bit to the next may be 
50% (1/2 LSB is a common measure for differential error), but if the DAC 
maker has held the integral nonlinearity error down, then that error will 
not propagate to the next LSB and the next.  Hence, scrambling and 
averaging may help.

Like I said, it'll take some experimentation and deep study of the data 
sheets.

-- 
My liberal friends think I'm a conservative kook.
My conservative friends think I'm a liberal kook.
Why am I not happy that they have found common ground?

Tim Wescott, Communications, Control, Circuits & Software
http://www.wescottdesign.com

"glen herrmannsfeldt" <gah@ugcs.caltech.edu> wrote:

> I remember a system from many years ago, designed to be faster than
> the then-current technology. It used a four bit ADC, four bit DAC,
> and then another four bit ADC. The signal went to the first ADC,
> the output went to the DAC, and then went to an analog subtractor
> to generate the input for the final ADC.

This is what is called "pipelined ADC". It is a common approach for high 
sampling rates and high resolution. Nonlinearity errors are usually 
corrected by LUT somewhere in the process.

VLV