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Pardon my last message. Something malfunctioned somewhere and only half of the message text was sent. I have a more burning question now. I am having trouble programming the control registers of the AD50 codec on the 5402 DSK. If anyone has succesfully programmed the codec on the 5402DSK could you please forward me the macro or code segment or point me in the direction of any example code? I am working with the c:\tieval22\examples\dsk5402\bios\audio example program that was installed with the current version of the full 54x Code Composer Studio 90-day trial. Has anyone else noticed that the PROGREG macro (exhibit A) that TI uses to program the codec in dss_dsk5402.s54 does not work? It may appear to work since the entire program does function as expected, however this is not due to any successful programming of the AD50's registers. This program just happens to work with the AD50 in its default state. I tested the PROGREG macro by using it to set the software power down bit in cntrl reg 1 which should disable audio output. It did not disable the audio output. Next, I wrote my own register programming code (exhibit B) inspired by spru173 pg 3-15. This does not work either and I don't know why. Hopefully I am testing the xrdy bit correctly. My understanding is that whichever McBSP1 register's sub-address I have at 48h, it's value can be accessed at 49h, right? The 3rd option I tried is to use codec_write_reg() of the Codec API from the board library dsk5402.lib. This would not build because both rts.lib and biosi.a54 define '_c_int00'. This makes me think that the Codec Api is not compatible with DSP/BIOS. Now I have about given up on programming the codec and any help would be greatly appreciated. (see code below) Thanks, Micah Exhibit A. PROGREG .macro progword ;; Using the hardware method of requesting ;; secondary communication to codec ;; Set FC to request secondary communications stm #dss_tmp, ar0 nop portr CPLD_CTRL2, *ar0 orm #CODEC1_FC_ON, *ar0 ;; that's #0x8 portw *ar0, CPLD_CTRL2 ;; write command stm #:progword:,DXR1_1 ;; clear FC stm #dss_tmp, ar0 nop portr CPLD_CTRL2, *ar0 andm #(~CODEC1_FC_ON), *ar0 portw *ar0, CPLD_CTRL2 ;; returns CPLD_CTRL2 to its state before macro ;; write 0 for next primary slot stm #0, DXR1_1 .endm Exhibit B. stm #0001h, SPSA ; SPSAHh nop nop wait_xrdy bitf SPAD, 0002h ; test 2nd bit at adress 49h (SPAD) bc wait_xrdy, NTC ; if xrdy=0 wait and take branch stm #1111h, DXR1_1 ; send 2ndary request (LSB=1) when xrdy=1 nop wait_xrdy2 bitf SPAD, 0002h ; test xrdy bit in SPCR2_1 bc wait_xrdy2, NTC ; if bit=0 wait=take branch stm #0000000101100000b, DXR1_1 ; send control word with s/w power down set nop nop wait_xrdy3 ; don't let the program continue until control ; word has been safely transmitted to ensure nothing ; can overwrite it bitf SPAD, 0002h bc wait_xrdy3, NTC nop nop __________________________________ |