> yes the DSP are connected together directly by wire,
nothing
> in middle, no fpga, but HRDY is wired to ARDY; no other
> device are connected to the EMIF. I tried to direct access
> the memory slave with a small program doing only this, but
> the result is worse : each read cycle takes around 360n;
> doing the same with DMA is 300n.
>
> I think the HPI access is very slow and there is nothing to
> do, reading the DSP manual (HPI timing, table 5-44) seems
> fast access is impossible!!!
Well maybe you're right. I would suggest posting your question on
TI's "Community" forum and see what they say. So
far TI is doing a good job on this, and they're very good about getting
back with some answer, even if not the one you
want.
If you do that please let me know, I'd like to follow your post and TI
replies and maybe chime in.
-Jeff
Reply by gbon...@tiscali.it●April 24, 20092009-04-24
Dear Jeff,
yes the DSP are connected together directly by wire, nothing in middle, no fpga,
but HRDY is wired to ARDY; no other device are connected to the EMIF. I tried to
direct access the memory slave with a small program doing only this, but the
result is worse : each read cycle takes around 360n; doing the same with DMA is
300n.
I think the HPI access is very slow and there is nothing to do, reading the DSP
manual (HPI timing, table 5-44) seems fast access is impossible!!!
Reply by Jeff Brower●April 23, 20092009-04-23
Gianluca-
> In a master /slave application with two 5502-300Mhz,
the master (via EMIF) read slave memory (throw its HPI). To
> speed-up the access, the EMIF is configured in 32bit access to avoid double
read. But the throughput is not very high,
> each read cycle (done by the master from DMA) is 300n. The EMIF configuration
is : TA=0, read setup=1, read strobe=3,
> read hold=1. If I reduce read strobe to 2 it doesn't work. I notice CS
signal is around 140n, that means the read
> operation is 140n and the other 160n is probably taken from master to save the
data.
> Is it possible increase the throutput ?? My target is read 1224 words in less
than 250micro, around 200n per word.
And you want to read/write *internal mem* of the slave 5502?
How did you wire up HRDY? To ARDY? Do you have anything else connected to
master EMIF?
Did you try making "brute force" CPU access? I.e. just a small program that
does nothing else? How fast can you get?
If you need optimal performance, my suggestion would be to optimize the HPI
access separately, using a microP, FPGA or
CPLD, then worry about EMIF + DMA. Otherwise it may be more confusing than
needed.
-Jeff
Reply by gbon...@tiscali.it●April 23, 20092009-04-23
In a master /slave application with two 5502-300Mhz, the master (via EMIF) read
slave memory (throw its HPI). To speed-up the access, the EMIF is configured in
32bit access to avoid double read. But the throughput is not very high, each
read cycle (done by the master from DMA) is 300n. The EMIF configuration is :
TA=0, read setup=1, read strobe=3, read hold=1. If I reduce read strobe to 2 it
doesn't work. I notice CS signal is around 140n, that means the read
operation is 140n and the other 160n is probably taken from master to save the
data.
Is it possible increase the throutput ?? My target is read 1224 words in less
than 250micro, around 200n per word.