Quoc Thang NGUYEN wrote:

>Dear all,
>
>I am trying to interface 2 D/A converters to the SPORT serial port of a
>ADSP-21065L on an EZ-Kit Lite board.
>The converters are located on a daughterboard approximately 6 inches away
>from the EMAFE connector where the serial port signals are tapped.
>The converters do not receive the serial signals directly. Instead, the
>serial signals are buffered by a SN74AHC245 fast TTL buffer on the
>daughterboard.
>To prevent pickup, the three signals (clock, frame and data) travel into
>coaxial cables, grounded at both ends.
>To prevent reflexions, the end of each serial cable that goes to the
>appropriate SN74AHC245 input pin is terminated with a 51 Ohm resistor in
>series with a 100 pF capacitor, going to ground.
>The whole thing transfers 32 bits of data to the DACs with a clock rate =
>DSP clock divided by 16 (or more), every 50 microseconds
>
>The problem:
>========
>1) In between transfers (50 usec), on the Data line, if the last level is
>LOW, the level never stays at 0V but keeps on creeping past +2V. I think
>this gives me an extra bit when the low level crosses the threshold of the
>buffer. I don't seem to have the same problem on the transfer frame signal.
>2) When the clock rate is close to that of the DSP, the clock signal looks
>awful.How can I get > 10 MHz on the clock line?
>
>Can anyone help?
>Thank you very much.
>
>
>
>
>
>  
>
In multi-channel mode the Sharc tri-states the transmit data line. This 
(plus the AC termination) may account for problem 1. However, an "extra" 
edge in the data should not be a problem, that's the clock's job. If the 
last data bit doesn't stick around long enough, you may have selected 
the wrong sync mode (long/short, early/late, or whatever they call it in 
this case).
I agree with the other response that series termination at source is 
usually more successful; be sure to evaluate the waveform at the 
receiving end because series termination does allow ONE reflection 
(ideally).

-- 
Kevin Hales
Catalpa Technology, Inc.
302 E. Davis St. Ste 211
Culpeper, VA 22701
540-727-8005

Here is a suggestion...
    Try series terminating the lines at the source end instead of the load
end.  The series terminator should be less than 50 ohms to compensate for the
output impedance of the SPORT lines.  Then put a moderate pull down on the load
end.  I would guess about 1K would do it but you may need to try something
different.  Please keep us (the news group and me via e-mail) posted as I am
going to be dealing with the same problem in a short time.
    Alternatively, you might add a moderate pull-down resistor in parralel with
your AC terminator.  I have not tried this, but it should work.  I just happen
to prefer DC terminators to AC terminators.

Thanks,
Theron J. Hicks

Quoc Thang NGUYEN wrote:

> Dear all,
>
> I am trying to interface 2 D/A converters to the SPORT serial port of a
> ADSP-21065L on an EZ-Kit Lite board.
> The converters are located on a daughterboard approximately 6 inches away
> from the EMAFE connector where the serial port signals are tapped.
> The converters do not receive the serial signals directly. Instead, the
> serial signals are buffered by a SN74AHC245 fast TTL buffer on the
> daughterboard.
> To prevent pickup, the three signals (clock, frame and data) travel into
> coaxial cables, grounded at both ends.
> To prevent reflexions, the end of each serial cable that goes to the
> appropriate SN74AHC245 input pin is terminated with a 51 Ohm resistor in
> series with a 100 pF capacitor, going to ground.
> The whole thing transfers 32 bits of data to the DACs with a clock rate =
> DSP clock divided by 16 (or more), every 50 microseconds
>
> The problem:
> ========
> 1) In between transfers (50 usec), on the Data line, if the last level is
> LOW, the level never stays at 0V but keeps on creeping past +2V. I think
> this gives me an extra bit when the low level crosses the threshold of the
> buffer. I don't seem to have the same problem on the transfer frame signal.
> 2) When the clock rate is close to that of the DSP, the clock signal looks
> awful.How can I get > 10 MHz on the clock line?
>
> Can anyone help?
> Thank you very much.

Dear all,

I am trying to interface 2 D/A converters to the SPORT serial port of a
ADSP-21065L on an EZ-Kit Lite board.
The converters are located on a daughterboard approximately 6 inches away
from the EMAFE connector where the serial port signals are tapped.
The converters do not receive the serial signals directly. Instead, the
serial signals are buffered by a SN74AHC245 fast TTL buffer on the
daughterboard.
To prevent pickup, the three signals (clock, frame and data) travel into
coaxial cables, grounded at both ends.
To prevent reflexions, the end of each serial cable that goes to the
appropriate SN74AHC245 input pin is terminated with a 51 Ohm resistor in
series with a 100 pF capacitor, going to ground.
The whole thing transfers 32 bits of data to the DACs with a clock rate =
DSP clock divided by 16 (or more), every 50 microseconds

The problem:
========
1) In between transfers (50 usec), on the Data line, if the last level is
LOW, the level never stays at 0V but keeps on creeping past +2V. I think
this gives me an extra bit when the low level crosses the threshold of the
buffer. I don't seem to have the same problem on the transfer frame signal.
2) When the clock rate is close to that of the DSP, the clock signal looks
awful.How can I get > 10 MHz on the clock line?

Can anyone help?
Thank you very much.