singhs21@hotmail.com (S Singh) wrote in message news:<9c5369f0.0309300705.38a6aaa@posting.google.com>...
> Hi Santosh,
> 
> Thanks for the explanation. 
> 
> Actually my question is on a particular implementation of T/2
> Fractionally spaced equalizer (FSE) and not on DFE.
> 
> This particular implementation is said to be an "efficient
> implementation of fractionally spaced equalizer" and briefly given
> (Block Diagram) in FIGURE 4 of the following document: ( please see
> the link below )
> 
> http://spsc.inw.tugraz.at/courses/asp/ws01/schwingshackl.pdf
>  

Hi ...,

I have gone through fig 4. I guess it is using zero-forcing(ZF)
solution.

My posting is quite similar to fig 6. But FSE block is different. 

In fact instead of pure decimation filter we use a two feedforward
filters;
estimate prefilter taps using MMSE criteria(ZF criteria not good for
noise
dominant case(low SNR).) and filter samples through them and combine.

Feedback filter is used to estimate the kernel equalizer taps.

So  we pass following information to kernel equlaizer(MAP/Viterbi)
-filtered samples
-new equalizer taps

I am sure you will find all these information in the second paper.So
it
is worth to see.

May be for XDSL, you may not need this complex FSE(Fig 6 or modified
FSE as described in second paper). So fig 4 could be very
useful - anyway check your requirements and decide!

Regards,
Santosh

 





> I am trying to understand and looking for more info on this
> implementation of FSE.
> 
> I am still looking for the answers and will go through the references
> you gave, I guess I have gone through the first one sometime back.
> 
> Regards
> 
> S. Singh
> 
> santosh.nath@ntlworld.com (santosh nath) wrote in message news:<6afd943a.0309291329.1ed4a98c@posting.google.com>...
> > singhs21@hotmail.com (S Singh) wrote in message news:<9c5369f0.0309282322.56b5a7ee@posting.google.com>...
> > > I am trying to understand the efficient implementation of FSE, briefly
> > > described in http://spsc.inw.tugraz.at/courses/asp/ws01/schwingshackl.pdf
> > > (Fig 4)
> > > As an example of T/2 FSE, what I understand is that it separates out
> > > even and odd sample streams and apply the Tapped Delay Line (TDL)
> > > adaptive filters separately. the output of both filters are added.
> > > My question is how it is an efficient implementation, in what term it
> > > is efficient, memory or cycles?
> > > How it is equivalent to ordinary implementation in which the down
> > > sampling is done at the output of the equalizer ( Only the alternate
> > > output samples are generated and every time the TDL are shifted by 2)?
> > 
> > Hi There,
> > Your questions can not be answered in short notes - an ordinary
> > decimation filter(probably you meant above) will give poor performance
> > for CCI and ACI
> > test cases. You need to implement a MMSE DFE "prefilter" (act as
> > decimator also where we combine the fractionally spaced  samples) to
> > get much improved performance.Packet based sytems like EDGE needs
> > "prefiler" to reduce the complexity of bit detection unit like Viterbi
> > or MAP equalizer .....
> > 
> > Fractionally spaced receiver(T/2) consumes most of its cycles at
> > "prefilter"
> > design;There are fast Cholesky prefilters these days mainly for
> > fractionally spaced receivers. There are many more routines to take in
> >  an efficient
> > implementation- there is obvious chance of memory overlaying as
> > equalizer
> > has mostly sequential structure. It is however required to know how
> > much memory
> > and cycles one is allocating for equalizer prior to feature
> > implementation.
> > 
> >  Looking at your requirements I would recommend if you could consult
> > following papers:
> > 
> > 1. Ungerboeck "Fractinally spaced equalizer ...",1976,Aug,IEEE trans
> > communication - the original paper for fractinally spaced receiver
> > 2. Al Dhahir et al  " Fast computation of channel-estimate based
> > equalizers in packet data transmission", IEEE Trans.Signal processing
> > ... 2462-2473, Nov. 1995 - one of the best papers to discuss MMSE DFE
> > based prefiler
> > for T & T/2 etc spaced equalizers. It also gives algorithm complexity
> > and implemenation support.
> > 
> > Hope that helps a little.
> > Santosh
> > 
> > 
> > 
> > > 
> > > Thanks in Advance
> > > 
> > > S Singh

Hi Santosh,

Thanks for the explanation. 

Actually my question is on a particular implementation of T/2
Fractionally spaced equalizer (FSE) and not on DFE.

This particular implementation is said to be an "efficient
implementation of fractionally spaced equalizer" and briefly given
(Block Diagram) in FIGURE 4 of the following document: ( please see
the link below )

http://spsc.inw.tugraz.at/courses/asp/ws01/schwingshackl.pdf
 
I am trying to understand and looking for more info on this
implementation of FSE.

I am still looking for the answers and will go through the references
you gave, I guess I have gone through the first one sometime back.

Regards

S. Singh

santosh.nath@ntlworld.com (santosh nath) wrote in message news:<6afd943a.0309291329.1ed4a98c@posting.google.com>...
> singhs21@hotmail.com (S Singh) wrote in message news:<9c5369f0.0309282322.56b5a7ee@posting.google.com>...
> > I am trying to understand the efficient implementation of FSE, briefly
> > described in http://spsc.inw.tugraz.at/courses/asp/ws01/schwingshackl.pdf
> > (Fig 4)
> > As an example of T/2 FSE, what I understand is that it separates out
> > even and odd sample streams and apply the Tapped Delay Line (TDL)
> > adaptive filters separately. the output of both filters are added.
> > My question is how it is an efficient implementation, in what term it
> > is efficient, memory or cycles?
> > How it is equivalent to ordinary implementation in which the down
> > sampling is done at the output of the equalizer ( Only the alternate
> > output samples are generated and every time the TDL are shifted by 2)?
> 
> Hi There,
> Your questions can not be answered in short notes - an ordinary
> decimation filter(probably you meant above) will give poor performance
> for CCI and ACI
> test cases. You need to implement a MMSE DFE "prefilter" (act as
> decimator also where we combine the fractionally spaced  samples) to
> get much improved performance.Packet based sytems like EDGE needs
> "prefiler" to reduce the complexity of bit detection unit like Viterbi
> or MAP equalizer .....
> 
> Fractionally spaced receiver(T/2) consumes most of its cycles at
> "prefilter"
> design;There are fast Cholesky prefilters these days mainly for
> fractionally spaced receivers. There are many more routines to take in
>  an efficient
> implementation- there is obvious chance of memory overlaying as
> equalizer
> has mostly sequential structure. It is however required to know how
> much memory
> and cycles one is allocating for equalizer prior to feature
> implementation.
> 
>  Looking at your requirements I would recommend if you could consult
> following papers:
> 
> 1. Ungerboeck "Fractinally spaced equalizer ...",1976,Aug,IEEE trans
> communication - the original paper for fractinally spaced receiver
> 2. Al Dhahir et al  " Fast computation of channel-estimate based
> equalizers in packet data transmission", IEEE Trans.Signal processing
> ... 2462-2473, Nov. 1995 - one of the best papers to discuss MMSE DFE
> based prefiler
> for T & T/2 etc spaced equalizers. It also gives algorithm complexity
> and implemenation support.
> 
> Hope that helps a little.
> Santosh
> 
> 
> 
> > 
> > Thanks in Advance
> > 
> > S Singh

singhs21@hotmail.com (S Singh) wrote in message news:<9c5369f0.0309282322.56b5a7ee@posting.google.com>...
> I am trying to understand the efficient implementation of FSE, briefly
> described in http://spsc.inw.tugraz.at/courses/asp/ws01/schwingshackl.pdf
> (Fig 4)
> As an example of T/2 FSE, what I understand is that it separates out
> even and odd sample streams and apply the Tapped Delay Line (TDL)
> adaptive filters separately. the output of both filters are added.
> My question is how it is an efficient implementation, in what term it
> is efficient, memory or cycles?
> How it is equivalent to ordinary implementation in which the down
> sampling is done at the output of the equalizer ( Only the alternate
> output samples are generated and every time the TDL are shifted by 2)?

Hi There,
Your questions can not be answered in short notes - an ordinary
decimation filter(probably you meant above) will give poor performance
for CCI and ACI
test cases. You need to implement a MMSE DFE "prefilter" (act as
decimator also where we combine the fractionally spaced  samples) to
get much improved performance.Packet based sytems like EDGE needs
"prefiler" to reduce the complexity of bit detection unit like Viterbi
or MAP equalizer .....

Fractionally spaced receiver(T/2) consumes most of its cycles at
"prefilter"
design;There are fast Cholesky prefilters these days mainly for
fractionally spaced receivers. There are many more routines to take in
 an efficient
implementation- there is obvious chance of memory overlaying as
equalizer
has mostly sequential structure. It is however required to know how
much memory
and cycles one is allocating for equalizer prior to feature
implementation.

 Looking at your requirements I would recommend if you could consult
following papers:

1. Ungerboeck "Fractinally spaced equalizer ...",1976,Aug,IEEE trans
communication - the original paper for fractinally spaced receiver
2. Al Dhahir et al  " Fast computation of channel-estimate based
equalizers in packet data transmission", IEEE Trans.Signal processing
... 2462-2473, Nov. 1995 - one of the best papers to discuss MMSE DFE
based prefiler
for T & T/2 etc spaced equalizers. It also gives algorithm complexity
and implemenation support.

Hope that helps a little.
Santosh



> 
> Thanks in Advance
> 
> S Singh