|
Hi Phillip First lets assume the DSP itself is in pretty good shape with good solid supplies. The #1 key to making JTAG or any synchronous device for that matter work is to make sure you have a clean clock signal with clean and stable signals at the time the clock edge occurs. Basically the signals that are being latched in can be the worlds ugliest, but they must be valid at the time the clock tells the logic to 'take the sample'. And... if the clock is messed up, well you get the picture. If you are wondering about the TCLK signal quality, try perterbing it a bit. The #2 thing to notice is that the JTAG TDI-TDO path is actually a loop. Look more carefully and you will see that as TDO leaves a device or the JTAG test pod that it is clocked out by TCLK... but this is TCLK-OUT, making TDO and TCLKOUT 'flow out' together and in phase. The remote device then clocks TDO into its TDI using this phase synchrounous clock. Now, looking at TDO you will see that this too is clocked out, but in this case with reference to what? Well, if there is only 1 device in the scan chain, you can simply loop the clock back. But what if the scan chain is physically long or has many devices? This is where local clock buffering (near the remote device) comes in since it now becomes synchronous to the local TDI/TDO data flow and the edges get cleaned a bit. My personal opinion is that adding a TCLK buffer to the TI chips would be a nice feature. OK, so maybe its how the device is being set up or used. - Is the clock rate correct (150MHz out is not correct) - Are *all* the power and ground lines adequately bypassed - Are the supply levels correct. Do they dip unexpectedly when a transient occurs. Maybe they generate an erroneous reset. - Are there any huge transients occuring on the bus or IO pins that could be causing conflicts (expect ~50mA/conflict) Hope this helps Keith Larson PS: A trick that I have used in the past to find flaky signals is to connect a 1-10K resistor to a signal generator (maybe through a coupling cap) and the go probing around the board to find signals that are easily disturbed. The idea is to inject a small 1-10mA AC current that upon seing the typical 30-50 ohm output impedance of a typical buffer will erode the buffers noise margin by some 30-500mV. Note that you should keep the signal generator level somewhat within the supply rails or clamp it with some diodes so that the min/max input levels are not exceeded. At 07:32 PM 12/3/03 -0000, you wrote: Hallo... I use 2 target boards (one in-house developed and one eZdsp). With the eZdsp target board the CodeComposer(JTAG) work well. With my target board. it works in 95% not correct. -Sometimes I get an error when I start the CC (trouble reading target dsp) -Sometimes I can start the CC. But if I "reset DSP" => CC will crash -Sometimes I can load my program to the dsp...and scroll in the DisAssembly window. But if I scroll to happy (5 or 6 times) CC will crash to. -Sometimes(ca. 2-5%) it works. My target board... It is really simple. Oscillator: H1/H2 looks OK JTAG Connector: TMS,EMU0 EMU1 pull up TRST pull down TCK wired to TCK_RET RDY => LOW RSV0 RSV1 HOLD => HIGH ...does somebody have an idea whats my problem....?? thank you..... +-----------+ |Keith Larson | |Member Group Technical Staff | |Texas Instruments Incorporated | | | | 281-274-3288 | | | | www.micro.ti.com/~klarson | |-----------+ | TMS320C3x/C4x/VC33 Applications | | | | TMS320VC33 | | The lowest cost and lowest power 500 w/Mflop | | floating point DSP on the planet! | +-----------+ |