>Hi everybody, > >I've got a problem with the DSP board we just designed, I hope you can help me on this one: > >The design is mainly based on the 6711DSK, same DSP (6711 150MHz), same SDRAM family >(MT48LC4M16A2-7E but CAS=2 instead of 3 on latest DSK) clock at 100MHz through the EMIF, CE0 is used. > >My board works well, except for the SDRAMs. I am able to fill entirely my SDRAM with data using Edit-> >Memory->Fill in CCS. Then i am able to read it by using File->Data->Save in CCS still. So far it's fine. > >Problem starts to occur when i want to load my program into SDRAM (my DSP internal mem is a 4-way cache), >this error occur : "Data Verification Fail at address 0x80000150. Please verify target memory and memory >map" > I always do a GEL reset before loading code... Also, does it work better if you close CCS, then load the code as the first thing you do (before opening any memory windows etc.)? I notice you are using CAS latency of 2 - have you done the SDRAM init comand *after* setting up the CAS latency register in the DSP, I seem to recall some TI sample code that does it the wrong way round, but they use the default of 3 cycles, so it doesn't matter. >I've been trying to debug this problem by optimizing the EMIF settings for SDRAM (SDCTL, SDTIM, SDEXT) >but i have been unsuccessfull so far. > >I begin to question the hardware design. But it's should be OK as the SDRAMs are directly connected to my >DSP, it's quite a straightforward design, and as i said based on the 6711DSK. > How are the signals looking on the PCB? You have testpoints right :-)? Hope that helps give you something to try! Cheers, Martin -- Martin Thompson BEng(Hons) CEng MIEE TRW Conekt Stratford Road, Solihull, B90 4AX. UK Tel: +44 (0)121-627-3569 - |